To give people without the reference manual at hand a chance to
understand how spare area is handled in the i.MX nand controller,
improve commenting, naming of variables and coding style.

No functional change intended.
Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
[baruch: declare oob_chunk_size; update comments; reword commit log]
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Remove static in front of ctrl. This variable should not be shared
between different instances of brcmnand_probe(), it should be local to
this function and stored on the stack.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The caller already adds a new line and in the other cases there is no
new line added.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

There are a few small hooks required for chips like BCM63138 and the
iProc family. Let's introduce those now.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>

BCM7xxx chips are supported entirely by the library code, since they use
generic irqchip interfaces and don't need any extra SoC-specific
configuration.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This core originated in Set-Top Box chips (BCM7xxx) but is used in a
variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and
iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it
to those architectures.

There are multiple revisions of this core throughout the years, and
almost every version broke register compatibility in some small way, but
with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0,
and v7.1. It's been tested on v5.0, v6.0, v6.1, v7.0, and v7.1 recently,
so there hopefully are no more lurking inconsistencies.

This patch adds just some library support, on which platform drivers can
be built.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>

These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.

If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

In preparation to enable ARCH_MMP on ARM64, a couple of fixes are needed
to build the pxa3xx_nand driver:

Legacy DMA will only used on ARM, so also make it condtional on
CONFIG_ARM.
__raw_{read,write}sl are not available on ARM64 or generically, so use
the readsl/writesl variants instead. Somewhat inconsistently,
{read,write}sl are inherently non-swapping with the generic version
using __raw_{read,write}l.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
[Brian: added one more __raw_readsl -> readsl]
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Now that the driver handles the FIFO draining in a threaded interrupt, we can
base our timeout on jiffies and sleeping, instead of using mdelay.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

return type of wait_for_completion_timeout is unsigned long not int. An
appropriately named unsigned long is added and the assignment fixed up.
This not only should help readability but also handles corner cases
properly.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

wait_for_completion_timeout does not return negative values so
result handling here does not need to check for negative return.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

As all four bytes are written in any case the memset() is in vain.
Signed-off-by: NRichard Weinberger <richard@nod.at>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: NFabian Frederick <fabf@skynet.be>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This statement was written with a cast-to-loff_t to be sure to have a
full 64-bit mask. However, we don't account for the fact that
'1 << this->bbt_erase_shift' might already overflow.

This will not be a problem in practice, since eraseblocks should never
be anywhere near 4GiB. But we can do this for completeness, and quiet
Coverity in the meantime. CID #1226806.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Don't leak this->bbt, and return early if check_create() fails. It helps
to have a single error path to avoid these problems.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This implementation detail is no longer needed outside of nand_bbt.c.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The diskonchip driver almost uses the default nand_base hooks as-is,
except that it provides custom on-flash BBT descriptors and avoids using
factory-marked bad blockers.

So let's refactor the BBT initialization code into a private 'late_init'
hook which handles all the private details. Note the usage of
NAND_SKIP_BBTSCAN, which allows us to defer the BBT scan until we've
prepared everything.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This is only an API consolidation and should make things more readable
it replaces var * HZ / 1000 by msecs_to_jiffies(var) which helps readability
and also handles all corner-cases properly.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

if atmel,pmecc-lookup-table-offset is not found in DT node, we don't
need to map the ROM table as we will build a runtime gf table anyway.
Reported-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

It's better to use a macro instead of just a number.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The Denali Controller IP does not support sub-page writes.
Signed-off-by: NGraham Moore <grmoore@opensource.altera.com>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

return type of wait_for_completion_timeout is unsigned long not int, this
patch uses the return value of wait_for_completion_timeout in the condition
directly rather than assigning it to an incorrect type variable.

The variable used for handling the return of wait_for_cmpletion_timeout
was int but should be unsigned long, where it was not in use for
anything else and the return value in case of completion (>0) is not
used it was removed and wait_for_completion_timeout() used directly in
the if condition.

To make the timeout values a bit simpler to read and also handle all of
the corner cases correctly the declarations are moved to
msecs_to_jiffies().

The timeout declaration cleanup is just for readability
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

In case of scan_bbt() failure, we should better propagate it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NHuang Shijie <shijie.huang@intel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

return type of wait_for_completion_timeout is unsigned long not int. The
return variable is renamed to reflect its use and the type adjusted to
unsigned long.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NHuang Shijie <shijie.huang@intel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Without this patch the timings are all set to 0 if not specified in the dts.
With this patch the driver falls back to use the defaults that are already
present in the driver and are known to work okay for some (older) boards.

Tested on a custom SPEAr600 based board.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

If a NAND device is not really present or pin muxes are not correctly
configured we can lock up the kernel waiting infinitely for NAND_STATUS
to be ready.

This can be easily reproduced on TI's DRA7-evm board by booting it
without NAND support in u-boot and disabling NAND pin muxes in the kernel.

Add timeout when waiting for NAND_CMD_RESET completion. As per ONFi v4.0
tRST can be upto 250ms for EZ-NAND and 5ms for raw NAND.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

We're not initializing the ooblen field. Our users don't care, since
they check that oobbuf == NULL first, but it's good practice to zero
unused fields out.

We can drop the NULL initializations since we're memset()ing the whole
thing.

Noticed by Coverity, CID #200821, #200822
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

TclsRising is always 1.

Caught by Coverity.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>

Coverity noticed that these 'ret' assignments weren't being used. Let's
use them.

Note that nand_lock() and nand_unlock() are still not officially used by
any drivers.

Coverity CIDs #1227054 and #1227037
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The PARAM command was long unimplemented and it probably wasn't
noticed because chip probing using only the few bytes returned by the
READID command are good enough in most cases to determine the chip in
use.

Still to notice such a shortcoming earlier in the future would be nice
in case it's something more vital.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The mxc-nand driver never supported the PARAM command to read out the
ONFI parameter page and so always relied on probing my manufacturer and
device id (as provided by the READID command).

This patch implements reading out the first parameter page copy at least
which should be good enough in practise.

This makes the boot log change from

	nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xb1
	nand: Micron NAND 128MiB 1,8V 16-bit

to
	nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xb1
	nand: Micron MT29F1G16ABBDAH4

on my machine.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The mxc-nand controller works pagewise and so usually only sends
commands to the flash chip with column == 0. A request with column != 0
from the upper layer is then fulfilled by indexing appropriately into the
device's RAM buffer.

To be able to access the ONFI marker at offset 0x20 in reply to the
READID command however it's invalid to read 32 bytes starting from
column 0.

So let the function used to send the address cycles send the column
address actually passed instead of 0 and fix all callers to pass 0
instead appropriately. Also add some warnings in case this patch changes
the drivers semantics.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

When the hardware operates in 16 bit mode it always reads 16 bits even
for operations that only have the lower 8 bits defined. So the upper
bits must be discarded. Do this in the read_byte callback instead of
when reading the NAND id to support reading byte wise more than 5 bytes
and at other occations (like reading the ONFI parameter page).
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

At least on i.MX25 (i.e. NFCv2) preset_v2 is called with mtd->writesize
== 0 that is before the connect flash chip is detected. It then
configures for 8 bit ECC mode which needs 26 bytes of OOB per 512 bytes
main section. For flashes with a smaller OOB area issuing a read page
command makes the controller stuck with this config.

Note that this currently doesn't hurt because the first read page
command is issued only after detection is complete and preset is called
once more.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>