Fixed compilation errors in case of non-KEXEC kernel
Rearranging code so that crashk_res gets updated.
- crashk_res is updated after mips_parse_crashkernel(),
   after resource_init(), which is after arch_mem_init().
- The reserved memory is actually treated as Usable memory,
   Unless we load the crash kernel, everything works.
Signed-off-by: NPrem Mallappa <pmallappa@caviumnetworks.com>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/5805/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

KDUMP: skip indirection page, as crashkernel has already copied to destination

[ralf@linux-mips.org: cosmetic changes.]
Signed-off-by: NPrem Mallappa <pmallappa@caviumnetworks.com>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5786/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This change corrects DECstation HRT calibration, by removing the following
bugs:

1. Calibration period selection -- HZ / 10 has been chosen, however on
   DECstation computers, HZ never divides by 10, as the choice for HZ is
   among 128, 256 and 1024.  The choice therefore results in a systematic
   calibration error, e.g. 6.25% for the usual choice of 128 for HZ:

   128 / 10 * 10 = 120

   (128 - 120) / 128 -> 6.25%

   The change therefore makes calibration use HZ / 8 that is always
   accurate for the HZ values available, getting rid of the systematic
   error.

2. Calibration starting point synchronisation -- the duration of a number
   of intervals between DS1287A periodic interrupt assertions is measured,
   however code does not ensure at the beginning that the interrupt has
   not been previously asserted.  This results in a variable error of e.g.
   up to another 6.25% for the period of HZ / 8 (8.(3)% with the original
   HZ / 10 period) and the usual choice of 128 for HZ:

   1 / 16 -> 6.25%

   1 / 12 -> 8.(3)%

   The change therefore adds an initial call to ds1287_timer_state that
   clears any previous periodic interrupt pending.

The same issue applies to both I/O ASIC counter and R4k CP0 timer
calibration on DECstation systems as similar code is used in both cases
and both pieces of code are covered by this fix.

On an R3400 test system used this fix results in a change of the I/O ASIC
clock frequency reported from values like:

I/O ASIC clock frequency 23185830Hz

to:

I/O ASIC clock frequency 24999288Hz

removing the miscalculation by 6.25% from the systematic error and (for
the individual sample provided) a further 1.00% from the variable error,
accordingly.  The nominal I/O ASIC clock frequency is 25MHz on this
system.

Here's another result, with the fix applied, from a system that has both
HRTs available (using an R4400 at 60MHz nominal):

MIPS counter frequency 59999328Hz
I/O ASIC clock frequency 24999432Hz
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5807/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

ERROR: "copy_from_user_page" [drivers/staging/lustre/lustre/libcfs/libcfs.ko] undefined!
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5808/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The Ralink RT3883 SoCs have a built-in PCI Host Controller
device. The patch adds a platform driver and device tree
binding documentation for that.

The patch also enables the HW_HAS_PCI config option. This
is required in order to be able to enable the PCI support.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5758/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The BMIPS5000 (Zephyr) processor utilizes instruction speculation. A
stale misprediction address in either the JTB or the CRS may trigger
a prefetch inside a region that is currently being used by a DMA engine,
which is not IO-coherent.  This prefetch will fetch a line into the
scache, and that line will soon become stale (ie wrong) during/after the
DMA.  Mayhem ensues.

In dma-default.c, the r10000 is handled as a special case in the same way
that we want to handle Zephyr.  So we generalize the exception cases into
a function, and include Zephyr as one of the processors that needs this
special care.
Signed-off-by: NJim Quinlan <jim2101024@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5776/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add a helper for reseting different devices on the SoC.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5804/
Patchwork: https://patchwork.linux-mips.org/patch/5797/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Override certain CPU features to help GCC to optimize
the generated code. Saves about 150KB in the vmlinux
image with a generic configuration.

     text    data     bss     dec     hex filename
  3824158  134820  234192 4193170  3ffb92 vmlinux.no-override
  3664054  138804  234192 4037050  3d99ba vmlinux.override
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5759/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Register a clock device for the SPI block of the
MT7620 SoC. The clock device will be used by the
SPI host controller driver to determine the base
clock of the controller.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5754/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The watchdog driver of the SoC uses the clk API to
get the clock associated with the watchdog device.
However the MT7620 specific setup code does not
register a clock for the watchdog device yet which
leads to the following error:

  rt2880_wdt: probe of 10000120.watchdog failed with error -2

Register a clock device for the watchdog in order to
avoid the error and make the watchdog usable.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5756/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The current code assumes that the peripheral clock always
runs at 40MHz which is not true in all configuration. The
peripheral clock can also use the reference clock instead
of the fixed 40MHz rate. If the reference clock runs at a
different rate, various peripheries are behaving incorrectly.

Additionally, the currectly calculated system clock is also
wrong. The actual value what the code computes is the rate
of the DRAM which can be different from the system clock.

Add new helper functions to get the rate of the different
clocks and use the correct values for the registered clock
devices.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5755/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Select the the EHCI and OHCI symbols.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5675/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Make the code print which of SDRAM, DDR1 or DDR2 was detected.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/5671/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Make plat_time_init() call clocksource_of_init() allowing the systick cevt
to load.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/5670/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent
of the SoC master clock. If we want to automatic frequency scaling to work we
need to use the systick timer as the clock source.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5669/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Adds a driver for the periodic timer found on Ralink SoC.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5682/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add a default built-in device tree for XLP2xx SoC. The new file
xlp_fvp.dts has updated entries for I2C and memory.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5705/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add USB intialization code to handle the new XLP2XX USB 3.0 block.
This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic
for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h
and xlp/nlm_hal.c is also updated for the new USB block.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5744/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

XLP2xx has a new I2C controller which has 4 buses connected to
it. Update the IO offset and IRQ mapping code to reflect this.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5707/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

On XLP2xx, wakeup code does not need to enable clock on the core.
Update xlp/wakeup.c to handle this.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5703/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add code to calculate the CPU and PIC frequency for XLP2XX SoCs.

Since the PIC frequency on XLP2XX can be configured, add a new macro
pic_timer_freq() to be used in netlogic/common/time.c.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: Ganesan Ramalingam <ganesanr@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5701/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The config7/config4 register has to be written on all the threads.
This does not cause any problems in XLP, but is needed for XLPII
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5700/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

XLP2XX is first in the series of 28nm XLPII processors.

The changes are to:
* Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c.
* Add a cpu_is_xlpii() function to check for XLPII processors.
* Update xlp_mmu_init() to use config4 to enable extended TLB.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5698/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The flash chipselects can span 32MB, fix this in the built-in device
tree.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5704/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Do not pass a memory section in the built-in DTB, and let the
boot code use the values from the DRAM BARs.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5699/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Read the memory from the Bridge DRAM BARs, if it is not passed in
from the device tree. This will allow us to remove memory configuration
from built in device trees.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5743/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The ath79 code uses static clock devices and
provides its own clk_{get,put} implementations.

Change the code to use dynamically allocated
clock devices and register the clocks within
the clkdev framework.

Additionally, remove the local clk_{get,put}
implementation. The clkdev framework has a
common implementation of those.

Also move the call of ath79_clock_init() from
plat_mem_init() to plat_time_init(). Otherwise
it would not be possible to use memory allocation
functions from ath79clock_init() becasuse the
memory subsystem is not yet initialized when
plat_mem_init() runs.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5780/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use local variables for ref, cpu, ddr and ahb
rates in SoC specific clock init functions.

The patch has no functional changes, it is
an interim change in preparation of the next
patch.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5781/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Instead of accessing the rate field of the static
clock devices directly, use the recently introduced
helper function to get the rate of the basic clocks.

The static ath79_{ahb,cpu,ddr,ref}_clk variables
will be removed by a subsequent patch. The actual
change is in preparation of that.

Also move the clock frequency printing code into
the plat_time_init function. We are getting the
cpu clock rate there already so we can save an
extra call of the helper.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5782/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The ath79 platform uses similar code to get the
rate of various clocks during init. Separate the
similar code into a new helper function and use
that to avoid code duplication.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5778/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The reference clock rate is passed in the first
argument of the function. Use that instead of the
rate of the global ath79_ref_clk variable.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5779/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The watchdog device on the AR933x is connected to
the AHB clock, however the current code uses the
reference clock. Due to the wrong rate, the watchdog
driver can't calculate correct register values for
a given timeout value and the watchdog unexpectedly
restarts the system.

The code uses the wrong value since the initial
commit 04225e1d
(MIPS: ath79: add AR933X specific clock init)

The patch fixes the code to use the correct clock
rate to avoid the problem.

Cc: stable@vger.kernel.org
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5777/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The ath79 code supports various SoCs which are using either a 24Kc
or a 74Kc core. The 74Kc core has DSP support, so don't hardwire
the values to zero.

Commit 00dc5ce2 (MIPS: ath79: don't
hardcode the unavailability of the DSP ASE) has fixed this already,
but that change got reverted by 47503256
(MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.)
Reported-by: NHelmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5750/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This add a default config for the Lantiq XWAY SoC.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5796/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The clocks of the serial ports were not setup properly.
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5659/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add cpu-feature-override.h for the GPON SoC
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5658/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This driver so far only reads the core voltage.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5677/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>