1. 21 11月, 2019 5 次提交
  2. 13 11月, 2019 1 次提交
    • V
      PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30 · 8181146c
      Vidya Sagar 提交于
      commit 7be142caabc4780b13a522c485abc806de5c4114 upstream.
      
      The PCI Tegra controller conversion to a device tree configurable
      driver in commit d1523b52 ("PCI: tegra: Move PCIe driver
      to drivers/pci/host") implied that code for the driver can be
      compiled in for a kernel supporting multiple platforms.
      
      Unfortunately, a blind move of the code did not check that some of the
      quirks that were applied in arch/arm (eg enabling Relaxed Ordering on
      all PCI devices - since the quirk hook erroneously matches PCI_ANY_ID
      for both Vendor-ID and Device-ID) are now applied in all kernels that
      compile the PCI Tegra controlled driver, DT and ACPI alike.
      
      This is completely wrong, in that enablement of Relaxed Ordering is only
      required by default in Tegra20 platforms as described in the Tegra20
      Technical Reference Manual (available at
      https://developer.nvidia.com/embedded/downloads#?search=tegra%202 in
      Section 34.1, where it is mentioned that Relaxed Ordering bit needs to
      be enabled in its root ports to avoid deadlock in hardware) and in the
      Tegra30 platforms for the same reasons (unfortunately not documented
      in the TRM).
      
      There is no other strict requirement on PCI devices Relaxed Ordering
      enablement on any other Tegra platforms or PCI host bridge driver.
      
      Fix this quite upsetting situation by limiting the vendor and device IDs
      to which the Relaxed Ordering quirk applies to the root ports in
      question, reported above.
      Signed-off-by: NVidya Sagar <vidyas@nvidia.com>
      [lorenzo.pieralisi@arm.com: completely rewrote the commit log/fixes tag]
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: NThierry Reding <treding@nvidia.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      8181146c
  3. 06 11月, 2019 2 次提交
    • S
      PCI/PME: Fix possible use-after-free on remove · a897f54e
      Sven Van Asbroeck 提交于
      [ Upstream commit 7cf58b79b3072029af127ae865ffc6f00f34b1f8 ]
      
      In remove(), ensure that the PME work cannot run after kfree() is called.
      Otherwise, this could result in a use-after-free.
      
      This issue was detected with the help of Coccinelle.
      Signed-off-by: NSven Van Asbroeck <TheSven73@gmail.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Sinan Kaya <okaya@kernel.org>
      Cc: Frederick Lawler <fred@fredlawl.com>
      Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
      Cc: Keith Busch <keith.busch@intel.com>
      Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      a897f54e
    • L
      PCI: Fix Switchtec DMA aliasing quirk dmesg noise · 33970cf5
      Logan Gunthorpe 提交于
      [ Upstream commit 742bbe1ee35b5699c092541f97c7cec326556bb1 ]
      
      Currently the Switchtec quirk runs on all endpoints in the switch,
      including all the upstream and downstream ports.  These other functions do
      not contain BARs, so the quirk fails when trying to map the BAR and prints
      the error "Cannot iomap Switchtec device".  The user will see a few of
      these useless and scary errors, one for each port in the switch.
      
      At most, the quirk should only run on either a management endpoint
      (PCI_CLASS_MEMORY_OTHER) or an NTB endpoint (PCI_CLASS_BRIDGE_OTHER).
      However, the quirk is useless except in NTB applications, so we will
      only run it when the class is PCI_CLASS_BRIDGE_OTHER.
      
      Switch to using DECLARE_PCI_FIXUP_CLASS_FINAL and only match
      PCI_CLASS_BRIDGE_OTHER.
      Reported-by: NStephen Bates <sbates@raithlin.com>
      Fixes: ad281ecf ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB")
      Signed-off-by: NLogan Gunthorpe <logang@deltatee.com>
      [bhelgaas: split SWITCHTEC_QUIRK() introduction to separate patch]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Doug Meyer <dmeyer@gigaio.com>
      Cc: Kurt Schwemmer <kurt.schwemmer@microsemi.com>
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      33970cf5
  4. 29 10月, 2019 1 次提交
  5. 18 10月, 2019 1 次提交
  6. 12 10月, 2019 2 次提交
  7. 08 10月, 2019 6 次提交
  8. 01 10月, 2019 1 次提交
  9. 21 9月, 2019 1 次提交
  10. 19 9月, 2019 1 次提交
  11. 16 9月, 2019 6 次提交
    • L
      PCI: Reset both NVIDIA GPU and HDA in ThinkPad P50 workaround · f193e022
      Lyude Paul 提交于
      [ Upstream commit ad54567ad5d8e938ee6cf02e4f3867f18835ae6e ]
      
      quirk_reset_lenovo_thinkpad_50_nvgpu() resets NVIDIA GPUs to work around
      an apparent BIOS defect.  It previously used pci_reset_function(), and
      the available method was a bus reset, which was fine because there was
      only one function on the bus.  After b516ea586d71 ("PCI: Enable NVIDIA
      HDA controllers"), there are now two functions (the HDA controller and
      the GPU itself) on the bus, so the reset fails.
      
      Use pci_reset_bus() explicitly instead of pci_reset_function() since it's
      OK to reset both devices.
      
      [bhelgaas: commit log, add e0547c81bfcf]
      Fixes: b516ea586d71 ("PCI: Enable NVIDIA HDA controllers")
      Fixes: e0547c81bfcf ("PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary")
      Link: https://lore.kernel.org/r/20190801220117.14952-1-lyude@redhat.comSigned-off-by: NLyude Paul <lyude@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NBen Skeggs <bskeggs@redhat.com>
      Cc: Lukas Wunner <lukas@wunner.de>
      Cc: Daniel Drake <drake@endlessm.com>
      Cc: Aaron Plattner <aplattner@nvidia.com>
      Cc: Peter Wu <peter@lekensteyn.nl>
      Cc: Ilia Mirkin <imirkin@alum.mit.edu>
      Cc: Karol Herbst <kherbst@redhat.com>
      Cc: Maik Freudenberg <hhfeuer@gmx.de>
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      f193e022
    • J
      PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code · 3f27a14b
      Jisheng Zhang 提交于
      [ Upstream commit e6fdd3bf5aecd8615f31a5128775b9abcf3e0d86 ]
      
      Use devm_pci_alloc_host_bridge() to simplify the error code path.  This
      also fixes a leak in the dw_pcie_host_init() error path.
      Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com>
      CC: stable@vger.kernel.org	# v4.13+
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      3f27a14b
    • L
      PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary · 0fe09701
      Lyude Paul 提交于
      [ Upstream commit e0547c81bfcfad01cbbfa93a5e66bb98ab932f80 ]
      
      On ThinkPad P50 SKUs with an Nvidia Quadro M1000M instead of the M2000M
      variant, the BIOS does not always reset the secondary Nvidia GPU during
      reboot if the laptop is configured in Hybrid Graphics mode.  The reason is
      unknown, but the following steps and possibly a good bit of patience will
      reproduce the issue:
      
        1. Boot up the laptop normally in Hybrid Graphics mode
        2. Make sure nouveau is loaded and that the GPU is awake
        3. Allow the Nvidia GPU to runtime suspend itself after being idle
        4. Reboot the machine, the more sudden the better (e.g. sysrq-b may help)
        5. If nouveau loads up properly, reboot the machine again and go back to
           step 2 until you reproduce the issue
      
      This results in some very strange behavior: the GPU will be left in exactly
      the same state it was in when the previously booted kernel started the
      reboot.  This has all sorts of bad side effects: for starters, this
      completely breaks nouveau starting with a mysterious EVO channel failure
      that happens well before we've actually used the EVO channel for anything:
      
        nouveau 0000:01:00.0: disp: chid 0 mthd 0000 data 00000400 00001000 00000002
      
      This causes a timeout trying to bring up the GR ctx:
      
        nouveau 0000:01:00.0: timeout
        WARNING: CPU: 0 PID: 12 at drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c:1547 gf100_grctx_generate+0x7b2/0x850 [nouveau]
        Hardware name: LENOVO 20EQS64N0B/20EQS64N0B, BIOS N1EET82W (1.55 ) 12/18/2018
        Workqueue: events_long drm_dp_mst_link_probe_work [drm_kms_helper]
        ...
        nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1)
        nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1)
        nouveau 0000:01:00.0: fifo: fault 01 [WRITE] at 0000000000008000 engine 00 [GR] client 15 [HUB/SCC_NB] reason c4 [] on channel -1 [0000000000 unknown]
      
      The GPU never manages to recover.  Booting without loading nouveau causes
      issues as well, since the GPU starts sending spurious interrupts that cause
      other device's IRQs to get disabled by the kernel:
      
        irq 16: nobody cared (try booting with the "irqpoll" option)
        ...
        handlers:
        [<000000007faa9e99>] i801_isr [i2c_i801]
        Disabling IRQ #16
        ...
        serio: RMI4 PS/2 pass-through port at rmi4-00.fn03
        i801_smbus 0000:00:1f.4: Timeout waiting for interrupt!
        i801_smbus 0000:00:1f.4: Transaction timeout
        rmi4_f03 rmi4-00.fn03: rmi_f03_pt_write: Failed to write to F03 TX register (-110).
        i801_smbus 0000:00:1f.4: Timeout waiting for interrupt!
        i801_smbus 0000:00:1f.4: Transaction timeout
        rmi4_physical rmi4-00: rmi_driver_set_irq_bits: Failed to change enabled interrupts!
      
      This causes the touchpad and sometimes other things to get disabled.
      
      Since this happens without nouveau, we can't fix this problem from nouveau
      itself.
      
      Add a PCI quirk for the specific P50 variant of this GPU.  Make sure the
      GPU is advertising NoReset- so we don't reset the GPU when the machine is
      in Dedicated graphics mode (where the GPU being initialized by the BIOS is
      normal and expected).  Map the GPU MMIO space and read the magic 0x2240c
      register, which will have bit 1 set if the device was POSTed during a
      previous boot.  Once we've confirmed all of this, reset the GPU and
      re-disable it - bringing it back to a healthy state.
      
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=203003
      Link: https://lore.kernel.org/lkml/20190212220230.1568-1-lyude@redhat.comSigned-off-by: NLyude Paul <lyude@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: nouveau@lists.freedesktop.org
      Cc: dri-devel@lists.freedesktop.org
      Cc: Karol Herbst <kherbst@redhat.com>
      Cc: Ben Skeggs <skeggsb@gmail.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      0fe09701
    • L
      PCI: Add macro for Switchtec quirk declarations · 5659dfca
      Logan Gunthorpe 提交于
      [ Upstream commit 01d5d7fa8376c6b5acda86e16fcad22de6bba486 ]
      
      Add SWITCHTEC_QUIRK() to reduce redundancy in declaring devices that use
      quirk_switchtec_ntb_dma_alias().
      
      By itself, this is no functional change, but a subsequent patch updates
      SWITCHTEC_QUIRK() to fix ad281ecf ("PCI: Add DMA alias quirk for
      Microsemi Switchtec NTB").
      
      Fixes: ad281ecf ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB")
      Signed-off-by: NLogan Gunthorpe <logang@deltatee.com>
      [bhelgaas: split to separate patch]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      5659dfca
    • B
      PCI: qcom: Don't deassert reset GPIO during probe · e1a12c3b
      Bjorn Andersson 提交于
      [ Upstream commit 02b485e31d98265189b91f3e69c43df2ed50610c ]
      
      Acquiring the reset GPIO low means that reset is being deasserted, this
      is followed almost immediately with qcom_pcie_host_init() asserting it,
      initializing it and then finally deasserting it again, for the link to
      come up.
      
      Some PCIe devices requires a minimum time between the initial deassert
      and subsequent reset cycles. In a platform that boots with the reset
      GPIO asserted this requirement is being violated by this deassert/assert
      pulse.
      
      Acquire the reset GPIO high to prevent this situation by matching the
      state to the subsequent asserted state.
      
      Fixes: 82a82383 ("PCI: qcom: Add Qualcomm PCIe controller driver")
      Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
      [lorenzo.pieralisi@arm.com: updated commit log]
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      e1a12c3b
    • B
      PCI: qcom: Fix error handling in runtime PM support · be905d0f
      Bjorn Andersson 提交于
      [ Upstream commit 6e5da6f7d82474e94c2d4a38cf9ca4edbb3e03a0 ]
      
      The driver does not cope with the fact that probe can fail in a number
      of cases after enabling runtime PM on the device; this results in
      warnings about "Unbalanced pm_runtime_enable". Furthermore if probe
      fails after invoking qcom_pcie_host_init() the power-domain will be left
      referenced.
      
      As it is not possible for the error handling in qcom_pcie_host_init() to
      handle errors happening after returning from that function the
      pm_runtime_get_sync() is moved to qcom_pcie_probe() as well.
      
      Fixes: 854b69ef ("PCI: qcom: add runtime pm support to pcie_port")
      Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
      [lorenzo.pieralisi@arm.com: updated commit log]
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      be905d0f
  12. 31 7月, 2019 8 次提交
  13. 26 7月, 2019 3 次提交
  14. 22 6月, 2019 1 次提交
  15. 15 6月, 2019 1 次提交