The Armada 7K/8K use the same RTC IP than the Armada 38x. However the SOC
integration differs in 2 points:
 - MBUS bridge timing initialization
 - IRQ configuration at SoC level

Moreover the Armada 7K/8K have an issue preventing to get the interrupt
from alarm 1. This commit allows to use alarm 2 for these A7K/8K but to
still use alarm 1 for the Armada 38x.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

In order to prepare the introduction of the A7K/A8K version of the RTC,
this commit introduces a new data structure. This structure allows to
handle the differences between the integration of the RTC IP in the
SoCs. It will be:
 - MBUS bridge timing initialization
 - IRQ configuration at SoC level
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Add the max_register  to the regmap_config definition. This allows
dumping of the device's registers via the regmap debugfs interface.
Signed-off-by: NPhil Reid <preid@electromag.com.au>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Whitespace was a combination of spaces and tabs.
Use spaces and align register / bit definitions.
Signed-off-by: NPhil Reid <preid@electromag.com.au>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

All users of this driver have been updated to allow the driver to
manage it's own resources and do the read/write operations internally.
The m48t86_ops are no longer used.

Remove the platform_data header and the support code in the driver.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The rtc-m48t86 driver can now handle it's own resources and do the
read/write operations internally.

Pass the necessary resources to the driver and remove the m48t86_ops
platform data.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-By: NAlexander Clouter <alex+kernel@digriz.org.uk>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The rtc-m48t86 driver now handles the RTC detection. Remove the
redundant code from the platform.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-By: NAlexander Clouter <alex+kernel@digriz.org.uk>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The rtc-m48t86 driver can now handle its own resources and do the
read/write operations internally.

Pass the necessary resources to the driver and remove the m48t86_ops
platform data.

Remove the, then unnecessary, static remapping for the registers.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The RTC is an optional feature at purchase time on some Technologic
Systems boards. Verify that it actually exists by checking if the
last two bytes of the NVRAM can be changed.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This RTC has 114 bytes of NVRAM. Provide access to it via a binary
sysfs 'nvram' attribute file.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Allow this driver to, optionally, manage it's own resources and do the
read/write operations if the platform does not provide them.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

For aesthetics. Shorten all the register names by removing '_REG' from all
of them.
This helps fix all the checkpatch.pl issues.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

There are currently two broken bindings descriptions for RTC:

maxim,ds3231.txt
pcf8563.txt

They broke because of a improper RST documentation conversion with
commit 8c27ceff ("docs: fix locations of several documents that got
moved") and now reference to a non-existing file:

Documentation/devicetree/bindings/i2c/trivial-admin-guide/devices.rst

However, the original reference to i2c/trivial-devices should have never
been made in the first place.

This change fixes this issue by replacing with correct descriptions.
Reported-by: NWolfram Sang <wsa@the-dreams.de>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

In case of error, the function of_io_request_and_map() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().

Fixes: 847b8bf62eb4 ("rtc: sun6i: Expose the 32kHz oscillator")
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

COMPILE_TEST was wrongly placed, move it to the "depends on" line.
Also depend on COMMON_CLK as the driver now needs it to be properly
compiled.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Commit 847b8bf62eb4 ("rtc: sun6i: Expose the 32kHz oscillator") adds
a new clock for the rtc block with a 2 step probe mechanism. To share
the register region between both the clock and rtc instance, a static
pointer is used to keep the related data structure.

To preserve compatibility with the old binding, the data structure
should be saved as soon as the registers are mapped in, regardless
of the presence of the clock bindings, so that the rtc device can
retrieve it when it is probed.

This fixes the rtc device not probing when we use the updated driver
with an old device tree blob.

Fixes: 847b8bf62eb4 ("rtc: sun6i: Expose the 32kHz oscillator")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The clear of the LPTA_EN flag should be synced before writing to the
alarm register. Omitting this synchronization creates a race when
trying to change existing alarm.
Signed-off-by: NGuy Shapiro <guy.shapiro@mobi-wize.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The bq32000 includes a trickle charge circuit to maintain the charge of the
backup supply when a super capacitor is used.

You can enable the charging circuit by setting 'trickle-resistor-ohms',
additionally you can set TCFE to 1 to bypass the internal diode and boost
the charge voltage of the backup supply. You might want to enable/disable
the TCFE switch from userspace (e.g when device is only connected to a
battery)

This patch introduces a new sysfs entry to enable and disable this FET
form userspace.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Now that we have a devm variant of rtc_device_register, switch to it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The RTC controls the input source of the main 32kHz oscillator in the
system, feeding it to the clock unit too.

By default, this is using an internal, very inaccurate (+/- 30%)
oscillator with a divider to make it roughly around 32kHz. This is however
quite impractical for the RTC, since our time will not be tracked properly.

Since this oscillator is an input of the main clock unit, and since that
clock unit will be probed using CLK_OF_DECLARE, we have to use it as well,
leading to a two stage probe: one to enable the clock, the other one to
enable the RTC.

There is also a slight change in the binding that is required (and should
have been from the beginning), since we'll need a phandle to the external
oscillator used on that board. We support the old binding by not allowing
to switch to the external oscillator and only using the internal one (which
was the previous behaviour) in the case where we're missing that phandle.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The RTC is clocked from either an internal, imprecise, oscillator or an
external one, which is usually much more accurate.

The difference perceived between the time elapsed and the time reported by
the RTC is in a 10% scale, which prevents the RTC from being useful at all.

Fortunately, the external oscillator is reported to be mandatory in the
Allwinner datasheet, so we can just switch to it.

Cc: stable@vger.kernel.org
Fixes: 9765d2d9 ("rtc: sun6i: Add sun6i RTC driver")
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Some registers have a read-modify-write access pattern that are not atomic.

Add some locking to prevent from concurrent accesses.

Cc: stable@vger.kernel.org
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Since we have to provide the clock very early on, the RTC driver cannot be
built as a module. Make sure that won't happen.

Cc: stable@vger.kernel.org
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This adds bindings and simple probing for the Cortina Systems Gemini
SoC RTC.

Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This patches fixes comparison between signed and unsigned values as it
could produce an incorrect result when the signed value is converted to
unsigned:

drivers/rtc/rtc-stm32.c: In function 'stm32_rtc_valid_alrm':
drivers/rtc/rtc-stm32.c:404:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  if ((((tm->tm_year > cur_year) &&
...

It also fixes comparison always true or false due to the fact that unsigned
value is compared against zero with >= or <:

drivers/rtc/rtc-stm32.c: In function 'stm32_rtc_init':
drivers/rtc/rtc-stm32.c:514:35: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits]
  for (pred_a = pred_a_max; pred_a >= 0; pred_a-- ) {

drivers/rtc/rtc-stm32.c:530:44: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
     (rate - ((pred_a + 1) * (pred_s + 1)) < 0) ?

Fixes: 4e64350f ("rtc: add STM32 RTC driver")
Signed-off-by: NAmelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Using the ~ operator on a BIT() constant results in a large 'unsigned long'
constant that won't fit into an 'unsigned int' function argument on 64-bit
architectures, resulting in a harmless build warning in x86 allmodconfig:

drivers/rtc/rtc-stm32.c: In function 'stm32_rtc_probe':
drivers/rtc/rtc-stm32.c:651:51: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
  regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, ~PWR_CR_DBP);

As PWR_CR_DBP mask prevents other bits to be cleared, replace all
~PWR_CR_DBP by 0.

Fixes: 4e64350f ("rtc: add STM32 RTC driver")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAmelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Accessing the registers of the RTC block on Tegra requires the module
clock to be enabled. This only works because the RTC module clock will
be enabled by default during early boot. However, because the clock is
unused, the CCF will disable it at late_init time. This causes the RTC
to become unusable afterwards. This can easily be reproduced by trying
to use the RTC:

	$ hwclock --rtc /dev/rtc1

This will hang the system. I ran into this by following up on a report
by Martin Michlmayr that reboot wasn't working on Tegra210 systems. It
turns out that the rtc-tegra driver's ->shutdown() implementation will
hang the CPU, because of the disabled clock, before the system can be
rebooted.

What confused me for a while is that the same driver is used on prior
Tegra generations where the hang can not be observed. However, as Peter
De Schrijver pointed out, this is because on 32-bit Tegra chips the RTC
clock is enabled by the tegra20_timer.c clocksource driver, which uses
the RTC to provide a persistent clock. This code is never enabled on
64-bit Tegra because the persistent clock infrastructure does not exist
on 64-bit ARM.

The proper fix for this is to add proper clock handling to the RTC
driver in order to ensure that the clock is enabled when the driver
requires it. All device trees contain the clock already, therefore
no additional changes are required.
Reported-by: NMartin Michlmayr <tbm@cyrius.com>
Acked-By Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The ordering of includes is currently completely arbitrary, making it
impossible to decide where to put new includes. Remove the dilemma by
sort the include list alphabetically.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The new driver has a stray #ifdef in it that causes a build error:

drivers/rtc/rtc-stm32.c:718:21: error: 'stm32_rtc_of_match' undeclared here (not in a function); did you mean 'stm32_rtc_pm_ops'?

As the #ifdef serves no purpose here, let's just remove it.

Fixes: 4e64350f ("rtc: add STM32 RTC driver")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The remove function can be called at runtime for a manual 'unbind'
operation and must not be left out from a built-in driver, as kbuild
complains:

`stm32_rtc_remove' referenced in section `.data.stm32_rtc_driver' of drivers/rtc/rtc-stm32.o: defined in discarded section `.exit.text' of drivers/rtc/rtc-stm32.o

This removes the extraneous annotation.

Fixes: 4e64350f ("rtc: add STM32 RTC driver")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This patch adds support for the STM32 RTC.
Signed-off-by: NAmelie Delaunay <amelie.delaunay@st.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This patch adds documentation of device tree bindings for the STM32 RTC.
Signed-off-by: NAmelie Delaunay <amelie.delaunay@st.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Armada38x wants to modify its rtc_class_ops to remove the interrupt
handling when there is no usable interrupt, but this means we leave
function pointers in writable memory.

Since rtc_class_ops is small, arrange to have two instances, one for
when we have interrupts, and one for when we have none, both marked
const.  This allows the compiler to place them in read-only memory,
which is better than placing them in __ro_after_init.

Thanks to Bhumika Goyal <bhumirks@gmail.com> for pointing out that
the structure was writable and submitting a patch to add
__ro_after_init.
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Declare rtc_class_ops structures as const as they are only passed
as an argument to the function devm_rtc_device_register. This argument
is of type const struct rtc_class_ops *, so rtc_class_ops structures
having this property can be declared const.
Done using Coccinelle:

@r1 disable optional_qualifier @
identifier i;
position p;
@@
static struct rtc_class_ops i@p = {...};

@ok1@
identifier r1.i;
position p;
@@
devm_rtc_device_register(...,&i@p,...)

@bad@
position p!={r1.p,ok1.p};
identifier r1.i;
@@
i@p

@depends on !bad disable optional_qualifier@
identifier r1.i;
@@
+const
struct rtc_class_ops i;
Signed-off-by: NBhumika Goyal <bhumirks@gmail.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Document the DryIce security violation interrupt.
Signed-off-by: NMartin Kaiser <martin@kaiser.cx>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

The DryIce chipset has a dedicated security violation interrupt that is
triggered for security violations (if configured to do so).  According
to the publicly available imx258 reference manual, irq 56 is used for
this interrupt.

If an irq number is provided for the security violation interrupt,
install the same handler that we're already using for the "normal"
interrupt.

imxdi->irq is used only in the probe function, make it a local variable.
Signed-off-by: NMartin Kaiser <martin@kaiser.cx>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This patch adds alarm support. This allows to configure the chip
to generate an interrupt when the alarm matches current time value.
Alarm can be programmed up to one year in the future
and is accurate to the second.
Signed-off-by: NEmil Bartczak <emilbart@gmail.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

This patch adds support for saving/loading weekday value from the chip.
Signed-off-by: NEmil Bartczak <emilbart@gmail.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

According to RES-3124064:

The device supports CPU write and read access to the RTC time register.
However, due to this restriction, read and write from/to internal RTC
register may fail.

Workaround:
General setup:
1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0)
   to value 0xFD4D4FFF
   Write RTC WRCLK Period to its maximum value (0x3FF)
   Write RTC WRCLK setup to 0x29
   Write RTC WRCLK High Time to 0x53 (default value)
   Write RTC Read Output Delay to its maximum value (0x1F)
   Mbus - Read All Byte Enable to 0x1 (default value)
2. Configure the RTC Test Configuration Register (offset 0xA381C) bit3
   to '1' (Reserved, Marvell internal)

For any RTC register read operation:
1. Read the requested register 100 times.
2. Find the result that appears most frequently and use this result
   as the correct value.

For any RTC register write operation:
1. Issue two dummy writes of 0x0 to the RTC Status register (offset
   0xA3800).
2. Write the time to the RTC Time register (offset 0xA380C).

This patch is based on the work of Shaker Daibes
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Fixes checkpatch.pl warning:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Signed-off-by: NVesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>