It is best practice to clear and mask all interrupts before
associating the IRQ, and this should be done after the clock
is enabled.

This corrects a bad result from zynq_fpga_ops_state on bootup
where left over latched values in INT_STS_OFFSET caused it to
report an unconfigured FPGA as configured.

After this change the boot up operating state for an unconfigured
FPGA reports 'unknown'.
Signed-off-by: NJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: NAlan Tull <atull@opensource.altera.com>
Acked-by: NMoritz Fischer <moritz.fischer@ettus.com>

socfpga uses mgr->dev for debug prints, there should be consistency
here, so standardize on that. The only other use was for dma
which can be replaced with mgr->dev.parent.
Signed-off-by: NJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: NAlan Tull <atull@opensource.altera.com>
Acked-by: NMoritz Fischer <moritz.fischer@ettus.com>

Function dev_err doesn't add a newline at the end of the string. This will
lead to a hard to read kernel log.
Signed-off-by: NJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Reviewed-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NAlan Tull <atull@opensource.altera.com>

This patch adds a minor change in the FPGA Manager API
to hold information that is specific to an FPGA image
file.  This change is expected to bring little, if any,
pain.  The socfpga and zynq drivers are fixed up in
this patch.

An FPGA image file will have particulars that affect how the
image is programmed to the FPGA.  One example is that
current 'flags' currently has one bit which shows whether the
FPGA image was built for full reconfiguration or partial
reconfiguration.  Another example is timeout values for
enabling or disabling the bridges in the FPGA.  As the
complexity of the FPGA design increases, the bridges in the
FPGA may take longer times to enable or disable.

This patch adds a new 'struct fpga_image_info', moves the
current 'u32 flags' to it.  Two other image-specific u32's
are added for the bridge enable/disable timeouts.  The FPGA
Manager API functions are changed, replacing the 'u32 flag'
parameter with a pointer to struct fpga_image_info.
Subsequent patches fix the existing low level FPGA manager
drivers.
Signed-off-by: NAlan Tull <atull@opensource.altera.com>
Acked-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Upon registering a FPGA Manager low level driver, FPGA Manager
core overwrites the platform drvdata pointer. Prior to this commit
zynq-fpga falsely relied on this pointer to still be valid at remove()
time.
Reported-by: NAlan Tull <atull@opensource.altera.com>
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Acked-by: NAlan Tull <atull@opensource.altera.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This gets rid of the code to strip away the header and byteswap,
as well as the check for the sync word.
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NJosh Cartwright <joshc@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This commit fixes the unbalanced clock handling, where
a failed probe would leave the clock with an enable count of -1.
Reported-by: NJosh Cartwright <joshc@ni.com>
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This commit adds FPGA Manager support for the Xilinx Zynq chip.
The code borrows some from the xdevcfg driver in Xilinx'
vendor tree.
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>