1. 28 9月, 2012 5 次提交
  2. 10 8月, 2012 1 次提交
  3. 07 8月, 2012 1 次提交
  4. 17 7月, 2012 9 次提交
  5. 02 7月, 2012 1 次提交
  6. 07 6月, 2012 1 次提交
  7. 04 6月, 2012 1 次提交
    • J
      iommu/amd: Cache pdev pointer to root-bridge · c1bf94ec
      Joerg Roedel 提交于
      At some point pci_get_bus_and_slot started to enable
      interrupts. Since this function is used in the
      amd_iommu_resume path it will enable interrupts on resume
      which causes a warning. The fix will use a cached pointer
      to the root-bridge to re-enable the IOMMU in case the BIOS
      is broken.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      c1bf94ec
  8. 23 3月, 2012 1 次提交
  9. 15 3月, 2012 2 次提交
  10. 09 3月, 2012 1 次提交
  11. 08 3月, 2012 1 次提交
  12. 01 3月, 2012 1 次提交
    • J
      iommu/amd: Split amd_iommu_init function · 8704a1ba
      Joerg Roedel 提交于
      The hardware-initializtion part of the AMD IOMMU driver is
      split out into a seperate function. This function can now be
      called either from amd_iommu_init() itself or any other
      place if the hardware needs to be ready earlier. This will
      be used to implement interrupt remapping for AMD.
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      8704a1ba
  13. 22 12月, 2011 2 次提交
  14. 12 12月, 2011 7 次提交
  15. 21 6月, 2011 1 次提交
  16. 06 6月, 2011 1 次提交
  17. 10 5月, 2011 1 次提交
  18. 12 4月, 2011 1 次提交
  19. 11 4月, 2011 1 次提交
  20. 07 4月, 2011 1 次提交
    • J
      x86/amd-iommu: Flush all internal TLBs when IOMMUs are enabled · 7d0c5cc5
      Joerg Roedel 提交于
      The old code only flushed a DTE or a domain TLB before it is
      actually used by the IOMMU driver. While this is efficient
      and works when done right it is more likely to introduce new
      bugs when changing code (which happened in the past).
      This patch adds code to flush all DTEs and all domain TLBs
      in each IOMMU right after it is enabled (at boot and after
      resume). This reduces the complexity of the driver and makes
      it less likely to introduce stale-TLB bugs in the future.
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      7d0c5cc5