Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.

Also at boot, if these GDSCs are found to be ON, we make sure we
vote for them before we inform the genpd framework about their
status. If genpd gets no users, it then disables (removes the vote)
them as part of genpd_poweroff_unused()
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.

In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.

While at it, also move away from using jiffies and use ktime APIs
instead for busy looping on status bits.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Along with the GDSC power switch, there is additional control
to either retain all memory (core and peripheral) within a given
powerdomain or to turn them off while the GDSC is powered down.
Add support for these by modelling a RET state where all
memory is retained and an OFF state where all memory gets turned
off.
The controls provided are granular enough to be able to support
various differnt levels of RET states, like a 'shallow RET' with all memory
retained and a 'deep RET' with some memory retained while some others
are lost. The current patch does not support this and considers
just one RET state where all memory is retained. Futher work, if
needed can support multiple different levels of RET state.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>