This patch adds support for Broadcom Cygnus audio PLL and leaf
clocks
Signed-off-by: NSimran Rai <ssimran@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The PLL loop filter/gain can be located in a separate register on some
SoCs.  Split these off into a separate variable, so that an offset can
be added if necessary.  Also, make the necessary modifications to the
Cygnus and NSP drivers for this change.
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The macros that are being used to initialize the values of the clk
structures should be all caps.  Find and replace all of them with their
relevant counterparts.
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>