These checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Change the
checks for == 0 and update the type.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Over time, some includes were copy pasted from other clocks drivers but are
not necessary.
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Use the regmap coming from syscon to access the registers instead of using
pmc_read/pmc_write. This allows to avoid passing the at91_pmc structure to
the child nodes of the PMC.

The final benefit is to have each clock register itself instead of having
to iterate over the children.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Mostly converted with the following semantic patch:

@@
struct clk_hw *E;
@@

-__clk_get_num_parents(E->clk)
+clk_hw_get_num_parents(E)
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: Chao Xie <chao.xie@marvell.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Acked-by: NTero Kristo <t-kristo@ti.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.

Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.

The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
[sboyd@codeaurora.org: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NRomain Perier <romain.perier@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The at91sam9n12 and at91sam9x5 usb clocks do not propagate rate
modification requests to their parents.
This causes a bug when the PLLB is left uninitialized by the bootloader
(PLL multiplier set to 0, or in other words, PLL rate = 0 Hz).

Implement the determinate_rate method and propagate the change rate
request to the parent clk.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: NBo Shen <voice.shen@atmel.com>
Tested-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

First check for rate == 0 in set_rate and round_rate to avoid div by zero.
Then, in order to get the closest rate, round all divisions to the closest
result instead of rounding them down.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

at91rm9200_clk_usb_set_rate might fail depending on the requested rate,
because the parent_rate / rate remainder is not necessarily zero.
Moreover, when rounding down the calculated rate we might alter the
divisor calculation and end up with an invalid divisor.

To solve those problems, accept a non zero remainder, and always round
division to the closest result.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: NAndreas Henriksson <andreas.henriksson@endian.se>
Tested-by: NAndreas Henriksson <andreas.henriksson@endian.se>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Test rate value before calculating the div value to avoid div by zero.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: NGaël PORTAY <gael.portay@gmail.com>
Tested-by: NGaël PORTAY <gael.portay@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The RM9200 USB clock is actually connected to a single parent (the PLLB)
on which we can apply a specific divider.
The USB clock divider does not allow for fine grained control on the USB
clock frequency, hence propagating the set_rate request to the parent is
the only choice we have to properly configure the USB clock rate.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: NGaël PORTAY <gael.portay@gmail.com>
Tested-by: NGaël PORTAY <gael.portay@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds new at91 usb clock implementation using common clk framework.
This clock is used to clock usb ports (ohci, ehci and udc).
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>