- 01 7月, 2011 2 次提交
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由 Tomi Valkeinen 提交于
OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Tomi Valkeinen 提交于
OMAP3430 requires an 96MHz clock to VENC's DAC, but no other OMAP needs it. Add a new feature, FEAT_VENC_REQUIRES_TV_DAC_CLK, which tells if the clock is needed on this platform, and use that feature in venc.c to decide if the clock needs enabling. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 23 5月, 2011 1 次提交
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由 Amber Jain 提交于
Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: NAmber Jain <amber@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 19 5月, 2011 1 次提交
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由 Ricardo Neri 提交于
CTS and N parameters are used to regenerate the audio clock from the TMDS clock at the HDMI sink. In OMAP4430 ES1.0 version the calculation of the CTS parameter is done by the HDMI IP (hardware mode) while in others it must be done by the HDMI driver (software mode). A DSS feature is used to indicate the HDMI driver which mode is used. Signed-off-by: NRicardo Neri <ricardo.neri@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 16 5月, 2011 1 次提交
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由 Archit Taneja 提交于
On OMAP3, the DSI module has 2 data lanes. On OMAP4, DSI1 has 4 data lanes and DSI2 has 2 data lanes. Introduce function dsi_get_num_data_lanes() which returns the number of data lanes on the dsi interface, introduce function dsi_get_num_data_lanes_dssdev() which returns the number of data lanes used by the omap_dss_device connected to the lanes. Use the DSI_GNQ register on OMAP4 to get the number of data lanes, modify dsi.c to use the number of lanes and the extra data lanes on DSI1. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 13 5月, 2011 1 次提交
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由 Archit Taneja 提交于
The DSI interface is represented as a platform device, using the DSI platform driver(dsi.c). The current DSI driver design is capable of running only one instance of a DSI device. On OMAP4, there are 2 very similar DSI modules which can be represented as instances of "omapdss_dsi" platform device. Add member "module" in "dssdev.phy.dsi" that tells us which DSI module's lanes the panel is connected to. Modify dsi.c functions to take the device's platform_device struct pointer, provide functions dsi_get_dsidev_from_dssdev() and dsi_get_dsidev_from_id() take the panel's omap_dss_device and module number respectively, and return the platform_device pointer. Currently, the dsi struct is declared globally and is accessed when dsi data is needed. The new pdev argument will be used later to provide the platform device's dsi related data. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 11 5月, 2011 5 次提交
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由 Tomi Valkeinen 提交于
OMAP3430 has RESETDONETXCLKESCx bits in the order following bitnumber order for lanes 0, 1, 2: 28, 27, 26. OMAP3630 and later have them in saner order: 24, 25, 26 (and 27, 28 for OMAP4). This patch adds a dss_feature that can be used to differentiate between those two orders of RESETDONETXCLKESCx bits. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Tomi Valkeinen 提交于
CIO LDO status check seems to be broken on OMAP3630+ chips, and it's also quite unclear what LDO status actually tells and when its status changes. This patch removes the whole check on the grounds that if there's a problem with the LDO, we should anyway catch the problem as we check the CIO power state and CIO reset status. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Archit Taneja 提交于
Change enum dss_clk_source to omap_dss_clock_source and move it to 'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning. These changes are done in order to specify the clock sources for DSS in the board file. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Archit Taneja 提交于
The following changes have changed from OMAP3 to OMAP4 DSI: -The register field DSI_PLL_FREQSEL in DSI_PLL_CONFIGURATION2 has been removed. -DCS_CMD_ENABLE and DCS_CMD_CODE bits have been moved from DSI_CTRL to DSI_VC_CTRLi, hence the control of the bits is available per VC. -DSI LDO powergood notification doesn't work on OMAP4. This is mentioned in OMAP4 errata revision 1.8(Errata 1.76). -OCP_WIDTH register field is included in DSI_VC_CTRL. -The SCP clock is also required to access DSI PLL registers Introduce dss features for these changes so that DSI runs on both OMAP3 and OMAP4. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Tomi Valkeinen 提交于
OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3) to not work properly. The bug prevents us from enabling DSI PLL power only to HS divider block. This patch adds a dss feature for the bug and converts POWER_ON_DIV requests to POWER_ON_ALL (0x2). Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 15 4月, 2011 1 次提交
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由 Tomi Valkeinen 提交于
OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3) to not work properly. The bug prevents us from enabling DSI PLL power only to HS divider block. This patch adds a dss feature for the bug and converts POWER_ON_DIV requests to POWER_ON_ALL (0x2). Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 15 3月, 2011 2 次提交
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由 Taneja, Archit 提交于
The DSI PLL parameters (regm, regn, regm_dispc, regm_dsi, fint) have different fields and also different Max values on OMAP3 and OMAP4. Use dss features to calculate the register fields and min/max values based on current OMAP revision. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Taneja, Archit 提交于
Create 2 functions dss_feat_get_param_min() and dss_feat_get_param_max() which return the minimum and maximum value of a parameter. Introduce a enum in dss_features called dss_range_param which contains parameters whose ranges we are interested in. Replace this with dss_feat_get_max_dss_fck() which is specific to the parameter DSS_FCK. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 11 3月, 2011 5 次提交
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由 Taneja, Archit 提交于
On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as: Lcd Pixel clock = DISPC_FCLK / lcd / pcd Where lcd and pcd are divisors in the DISPC_DIVISOR register. On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as: Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2 Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers. LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL and DSI2 PLL as clock sources respectively. Introduce functions to select and get the clock source for these new clocks. Modify DISPC functions get the correct lck and pck rates based on the clock source of these clocks. Since OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source as DSS_CLK_SRC_FCK by introducing a dss feature. Introduce clock source names for OMAP4 and some register field changes in DSS_CTRL on OMAP4. Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as clock. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Murthy, Raghuveer 提交于
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div) field. The lcd_div is common, for deciding the DISPC core functional clock frequency, and the final pixel clock frequency for LCD display. In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR. The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core functional clock configuration. For pixel clock configuration of primary and secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used respectively Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Archit Taneja 提交于
Clock source names vary across OMAP2/3 and OMAP4, the clock source enum names have been made generic in the driver, but for purposes of debugging and dumping clock sources, it is better to preserve the actual TRM name of the clock. Introduce a dss feature function 'dss_feat_get_clk_source_name()' which returns a string with the TRM clock name for the current OMAP in use. The OMAP specific name is printed along the generic name within brackets. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Archit Taneja 提交于
The maximum supported frequency for DSS has increased from 173 to 186 Mhz on OMAP4. Introduce a dss feature function to get the max_fck to replace DISPC_MAX_FCK macro. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Archit Taneja 提交于
Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 10 1月, 2011 3 次提交
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由 Archit Taneja 提交于
Initialize a dss_features struct for omap4. Add support for LCD2 manager by introducing a new member in dss_feat_id. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>
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由 Archit Taneja 提交于
The supported set of color modes varies for different DISPC pipelines(plane) and omap version. This makes the checks for validation of a color mode more complicated as new omap versions are added. A dss_feature function is created which tells if a color_mode is supported for a plane on the current omap revision. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>
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由 Samreen 提交于
Splitting the OMAP3 dss has feature separately for omap3430 & omap3630 Signed-off-by: NSamreen <samreen@ti.com> Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>
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- 23 10月, 2010 1 次提交
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由 Archit Taneja 提交于
Add dss_features.c and dss_features.h for the dss_features framework. This framework will be used to move all cpu_is_xxx() and similar calls to a single place. Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>
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