- 16 8月, 2015 3 次提交
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由 Hai Li 提交于
Reset DSI PHY silently changes its PLL registers to reset status, which will make cached status in clock driver invalid and result in wrong output rate of link clocks. The current restore mechanism in DSI PLL does not cover all the cases. This change is to recover PLL status after PHY reset to match HW status with cached status in clock driver. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Hai Li 提交于
DSI controller on msm8x94 is version 1.3, which requires different power supplies and works with 20nm DSI PHY. This change is to add the basic support for this version. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Hai Li 提交于
The source PLL to be used by each DSI PHY should be decided by DSI manager based on dual DSI information, while the register programming to select PLL is different from one type of PHY to another. This change adds the H/W difference to PHY configuration and updates the interface between DSI manager and PHY. With this change, PLL selection can be supported on different targets. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 12 6月, 2015 3 次提交
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由 Hai Li 提交于
There are different types of PHY from one chipset to another, while the DSI host controller is relatively consistent across platforms. Also, the PLL inside PHY is providing the source of DSI byte and pixel clocks, which are used by DSI host controller. Separated devices for clock provider and clock consumer make DSI driver better fit into common clock framework. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Hai Li 提交于
This change activates PLL driver for DSI to work with common clock framework. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Hai Li 提交于
DSI byte clock and pixel clocks are sourced from DSI PLL. This change adds the DSI PLL source clock driver under common clock framework. This change handles DSI 28nm PLL only. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NWentao Xu <wentaox@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 02 4月, 2015 1 次提交
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由 Hai Li 提交于
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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