It's widely seen a MCE non-fatal error reported after resume.  It seems MCE
resume is lacked under ia32.  This patch tries to fix the gap.
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Acked-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Every file should #include the header files containing the prototypes of
its global functions
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Every file should #include the header files containing the prototypes of
its global functions
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Every file should #include the header files containing the prototypes of
its global functions
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Excerpt from bugzilla entry

http://bugzilla.kernel.org/show_bug.cgi?id=5518

"i386 version of Reboot-through-BIOS is unsafe: it forgets to mask APIC LVT
interrupts before jumping to a BIOS entry point.  As a result, BIOS ends up
bombarded with interrupts early on boot.  The BIOS does not expect it since
following a "normal" hardware cpu reset, all APIC LVT registers have the
Mask bit (16) set and can't generate interrupts.

For example, the version of Phoenix BIOS used by VMware enables interrupts
for the first time before masking/clearing APIC LVT.  The APIC Timer LVT
register is still set up for a timer interrupt delivery with a high vector
from the previous Linux incarnation (0xef in our case).  The BIOS has not
fully initialized its IDT at this point and the real mode gate for 0xef
remains all zeros.  Vector 0xef dispatches BIOS to address 0:0, BIOS takes
a #GP and eventually hangs.

machine_shutdown() does attempt to shut down APIC before jumping to BIOS,
but it is ineffective"
Signed-off-by: NZwane Mwaikambo <zwane@arm.linux.org.uk>
Cc: "Seth, Rohit" <rohit.seth@intel.com>
Cc: Zachary Amsden <zach@vmware.com>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Use ARRAY_SIZE macro instead of sizeof(x)/sizeof(x[0])
Signed-off-by: NTobias Klauser <tklauser@nuerscht.ch>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

SH7705 in extended cache mode has some left-over VALID_PAGE() cruft that it
checks when doing lazy dcache write-back.  This has been gone for some time
(the last bits were in the discontig code, which should now also be gone --
this also fixes up a build error in the non-discontig case).

pfn_valid() gives the desired behaviour, so we switch to that.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

There was only one board using this (hp690 specifically), and it just so
happens that it's only physically discontiguous at the "normal" P1 offset.  If
we bump up the P1 offset, it's possible to hit a shadowed region of memory
where we suddenly become magically contiguous.

As people have been using this shadowed region workaround for quite some time
(and without any adverse effects), it's time to drop the left over discontig
bits that no longer have any practical use (it was always very much
hp690-centric to begin with).
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This adds support for the relatively quirky (ie, not in line with any known
documentation, and amazed it works at all) SuperHyway implementation on
SH4-202.  This depends on the earlier SuperHyway patch for multiple block
support and VCR refactoring.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

sh had its own support for embedding ramdisk images in to the kernel binary,
but people are using initramfs for this now, so we drop the ramdisk embedding.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Kconfig patch needed by fs_enet to work.  Works like CONFIG_CPM2.

Cc: Kumar <kumar.gala@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This missing initrd header slipped though last time.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NMatt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

On PPC405GP/GPR it should be possible to enable PCI support, even when the
internal PCI arbiter is disabled (e.g.  when using an external PCI
arbiter).  The removed code didn't allow this, and also generated a warning
on PPC405EP platforms.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NMatt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Cleanup PPC40x eval boards (bubinga, walnut and sycamore) to support U-Boot
as bootloader.  The OpenBIOS bd_info struct is not used in the kernel
anymore (only U-Boot now).

uImage (U-Boot) tested on walnut, sycamore and bubinga
zImage (OpenBIOS) tested on sycamore, bubinga and ebony
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NMatt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Add support for AMCC PowerPC 440SPe "Yucca" eval board platform.
Signed-off-by: NRoland Dreier <rolandd@cisco.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Add support for the AMCC PowerPC 440SPe SoC, including PCI Express in root
port mode.
Signed-off-by: NRoland Dreier <rolandd@cisco.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

The PowerPC 440SP SoC has two Processor Local Bus (PLB) segments (a
high-throughput segment and a low-latency segment).  Fix our PLB register
definitions to cope with this, and add code to dump the status of both
segments when a machine check occurs.
Signed-off-by: NRoland Dreier <rolandd@cisco.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers
are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440
chips.  To allow for this, this patch moves the definition of the ERPN used
for mapping UART0 from being hard-coded in the head_44x.S assembly code to
being defined in ibm44x.h.
Signed-off-by: NRoland Dreier <rolandd@cisco.com>
Signed-off-by: NMatt Porter <mporter@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This patch adds watchdog, RTC support for Marvell EV64360BP board.
Signed-off-by: NLee Nicks <allinux@gmail.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Oops, some last minute changes caused the 64K pages patch to break ppc32
build, this fixes it.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

The zImage wrapper has a bug where it doesn't claim() the memory for the
kernel properly, it forgets to take into account the offset between the ELF
header and the kernel itself.  This results on some machines, like G5s,
into a kernel that crashes at boot when clearing the BSS.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Two CONFIG_SMP=n build fixes due to missing <asm/smp.h> includes.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

The current ia64 implementation of dma_get_cache_alignment does not work
for modules because it relies on a symbol which is not exported.  Direct
access to a global is a little ugly anyway, so this patch re-implements
dma_get_cache_alignment in a manner similar to what is currently used for
x86_64.
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).

The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad) due to a misunderstanding of the
srd instruction's behaviour (mea culpa).  The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.

In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible.  Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage).  With this patch, any given address is
governed by a single bitmap.  Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity).  Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set.  Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).

To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0].  As such, this patch also addresses a
hugepage problem introduced by that patch.  That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB.  This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).

Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).

[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diffSigned-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Adds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel
base page size to 64K.  The resulting kernel still boots on any
hardware.  On current machines with 4K pages support only, the kernel
will maintain 16 "subpages" for each 64K page transparently.

Note that while real 64K capable HW has been tested, the current patch
will not enable it yet as such hardware is not released yet, and I'm
still verifying with the firmware architects the proper to get the
information from the newer hypervisors.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

glibc expects to count lines beginning with "processor" to determine
the number of processors, not lines beginning with "Processor".  So,
give glibc the format it expects.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We don't want to call dump_cpu_info() from cpu_init() after boot since
it produces a lot of unnecessary noise - since cpu_init() gets called
on resume and hotplug cpu insertion events.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Richard Purdie

Update the PXA pm.c file to allow machines (such as the Sharp
Zaurus) to override the standard pm functions but reuse/wrap them
where needed.

The init call is made slightly earlier to give machine code an init
level to override them in removing any race.

Signed-off-by: Richard Purdie
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Nicolas Pitre

Since we know the value of cpsr on entry, we can replace the bic+orr with
a single eor.  Also remove a possible result delay (at least on XScale).
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Lennert Buytenhek

Make the uengine loader use ixp2000_reg_wrb in the right places.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Alessandro Zummo

  This patch fixes AHB/PCI endianness problems when the
 processor is in little-endian mode.

 The patch configures the CSR register closely following the directives
 in [1], paragraph 4.1, page 19.

 According to the considerations in [1], page 11, while the AHB bus
 supports both endian modes, on the IXP4XX it always uses big-endian.

 The PCI bus is connected to the South AHB. A wrong setting in the CSR
 register will thus cause a malfunctional PCI bus.

 A schematic diagram of the bus interconnections on the IXP4XX
 can be found in [1], page 18.

 The patch has been verified to work on the NSLU2 in
 both LE and BE modes.

 The author is Peter Korsgaard.

 [1] Intel® IXP4XX Product Line of Network Processors and IXC1100
 Control Plane Processor:
 Understanding Big Endian and Little Endian Modes

 http://www.intel.com/design/network/applnots/25423701.pdfSigned-off-by: NAlessandro Zummo <a.zummo@towertech.it>
Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Dirk Opfer

This patch adds basic machine support for the Sharp SL-6000x (Tosa) PDAs.

Signed-off-by: Dirk Opfer
Signed-off-by: NRichard Purdie <rpurdie@rpsys.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

my patch "x86: initialise tss->io_bitmap_owner to something" (commit ID
d5cd4aad) introduced a problem with a
program (DOSEMU) that called ioperm after already doing some port i/o.

The problem is that a process switch return causes tss->io_bitmap_base
to be set to IO_BITMAP_OFFSET so that the fault (that *really* sets the
io bitmap) never triggers.

This fixes that regression.
Signed-off-by: NBart Oldeman <bartoldeman@users.sourceforge.net>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

We can't currently use asm-ppc/page.h in vmlinux.lds.S, so until
we have a merged page.h, define PAGE_SIZE and KERNELBASE locally.
Also gets rid of some dynamic executable cruft that we had for
32-bit.  With -Ttext=$(KERNELBASE) this didn't cause any problem,
but when we changed to putting . = KERNELBASE in the vmlinux.lds.S
this cruft caused the text to get linked at 0xa0 instead of
0xc0000000.  Oops.
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This also moves setup_cpu_maps to setup-common.c (calling it
smp_setup_cpu_maps) and uses it on both 32-bit and 64-bit.
Signed-off-by: NPaul Mackerras <paulus@samba.org>

No longer maintained

Patch from Nicolas Pitre

We have an optimized sha1 routine (arch/arm/lib/sha1.S) meant to
override the generic one in lib/sha1.c.

Unfortunately lib/lib.a is listed _before_ arch/arm/lib/lib.a in the
link argument list and therefore the architecture specific lib functions
are not picked up before the generic versions.

This patch is a quick fix to change that ordering for ARM.  Here's what
the kbuild maintainer had to say about it (was also CC'd on lkml):

On Wed, 2 Nov 2005, Sam Ravnborg wrote:
> This looks like an obvious way to achive correct ordering.
> We could change it so arch defines always took precedence but
> the above is so simple that it is not worth the effort.
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Todd Poynor

Add platform devices for flash to Lubbock and Mainstone board files.
Once in place, the two existing mtd map drivers for the boards will be
converted to use a single pxa2xx map driver in the linux-mtd tree.
Take 4: flash_platform_data .map_name vs. .name cleaned up, resync with
merged irda patch context.
Signed-off-by: NTodd Poynor <tpoynor@mvista.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>