1. 31 3月, 2011 1 次提交
  2. 30 3月, 2011 1 次提交
  3. 26 3月, 2011 1 次提交
  4. 11 3月, 2011 3 次提交
    • C
      arch/tile: support 4KB page size as well as 64KB · 76c567fb
      Chris Metcalf 提交于
      The Tilera architecture traditionally supports 64KB page sizes
      to improve TLB utilization and improve performance when the
      hardware is being used primarily to run a single application.
      
      For more generic server scenarios, it can be beneficial to run
      with 4KB page sizes, so this commit allows that to be specified
      (by modifying the arch/tile/include/hv/pagesize.h header).
      
      As part of this change, we also re-worked the PTE management
      slightly so that PTE writes all go through a __set_pte() function
      where we can do some additional validation.  The set_pte_order()
      function was eliminated since the "order" argument wasn't being used.
      
      One bug uncovered was in the PCI DMA code, which wasn't properly
      flushing the specified range.  This was benign with 64KB pages,
      but with 4KB pages we were getting some larger flushes wrong.
      
      The per-cpu memory reservation code also needed updating to
      conform with the newer percpu stuff; before it always chose 64KB,
      and that was always correct, but with 4KB granularity we now have
      to pay closer attention and reserve the amount of memory that will
      be requested when the percpu code starts allocating.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      76c567fb
    • C
      arch/tile: add some more VMSPLIT options and use consistent naming · 09c17eab
      Chris Metcalf 提交于
      This renames 3G_OPT to 2_75G, and adds 2_5G and 2_25G.
      
      For memory-intensive applications that are also network-buffer
      intensive it can be helpful to be able to tune the virtual address
      of the start of kernel memory.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      09c17eab
    • C
      arch/tile: fix some comments and whitespace · 5fb682b0
      Chris Metcalf 提交于
      This is a grab bag of changes with no actual change to generated code.
      This includes whitespace and comment typos, plus a couple of stale
      comments being removed.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      5fb682b0
  5. 24 2月, 2011 1 次提交
  6. 21 1月, 2011 3 次提交
  7. 25 11月, 2010 1 次提交
    • C
      pci root complex: support for tile architecture · f02cbbe6
      Chris Metcalf 提交于
      This change enables PCI root complex support for TILEPro.  Unlike
      TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI
      support consists of hypervisor upcalls for PIO, DMA, etc.  However,
      the performance is fine for the devices we have tested with so far
      (1Gb Ethernet, SATA, etc.).
      
      The <asm/io.h> header was tweaked to be a little bit more aggressive
      about disabling attempts to map/unmap IO port space.  The hacky
      <asm/pci-bridge.h> header was rolled into the <asm/pci.h> header
      and the result was simplified.  Both of the latter two headers were
      preliminary versions not meant for release before now - oh well.
      
      There is one quirk for our TILEmpower platform, which accidentally
      negotiates up to 5GT and needs to be kicked down to 2.5GT.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      f02cbbe6
  8. 29 10月, 2010 1 次提交
  9. 28 10月, 2010 1 次提交
  10. 16 10月, 2010 1 次提交
  11. 15 10月, 2010 1 次提交
  12. 07 7月, 2010 1 次提交
    • C
      arch/tile: Add driver to enable access to the user dynamic network. · 9f9c0382
      Chris Metcalf 提交于
      This network (the "UDN") connects all the cpus on the chip in a
      wormhole-routed dynamic network.  Subrectangles of the chip can
      be allocated by a "create" ioctl on /dev/hardwall, and then to access the
      UDN in that rectangle, tasks must perform an "activate" ioctl on that
      same file object after affinitizing themselves to a single cpu in
      the region.  Sending a wormhole-routed message that tries to leave
      that subrectangle causes all activated tasks to receive a SIGILL
      (just as they would if they tried to access the UDN without first
      activating themselves to a hardwall rectangle).
      
      The original submission of this code to LKML had the driver
      instantiated under /proc/tile/hardwall.  Now we just use a character
      device for this, conventionally /dev/hardwall.  Some futures planning
      for the TILE-Gx chip suggests that we may want to have other types of
      devices that share the general model of "bind a task to a cpu, then
      'activate' a file descriptor on a pseudo-device that gives access to
      some hardware resource".  As such, we are using a device rather
      than, for example, a syscall, to set up and activate this code.
      
      As part of this change, the compat_ptr() declaration was fixed and used
      to pass the compat_ioctl argument to the normal ioctl.  So far we limit
      compat code to 2GB, so the difference between zero-extend and sign-extend
      (the latter being correct, eventually) had been overlooked.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      9f9c0382
  13. 05 6月, 2010 1 次提交