Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register is set. This happened at least
on GM206 when running glmark2-drm.

While we are at it, use the more compact nvkm_wait_msec() to wait for
the bit to clear.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

v2: remove unneeded pci check
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

v2: remove error and only set link for pcie devices
v6: remove check for pcie device
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

v2: rename functions
v3: remove pcie2 accessors
v6: fix alignement and line width, also remove useless code
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

v5: don't set kepler func pointers
v6: fix alignment and line length

v5: don't set fermi or kepler func pointers
v6: fix alignment

v2: rename and group functions
v4: change copyright information
    move printing of pcie speeds into oneinit,
    rename all pcie functions to nvkm_pcie_*
    don't try to raise the pcie version when no higher one is supported
v5: revert Copyright changes and rename nvkm_pcie_raise_version to nvkm_pcie_set_version
v6: remove some useless pci_is_pcie checks and rework messages
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

From DCB 4.1 spec.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Differences from GM10x:
- GM20x LTC count detection differs from GM10x
- GM20x init doesn't require large page size setting
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

resman and nvgpu both do this, presumably for good reason.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

GM20x doesn't require the priv ring timeout bumps that GK/GM10x have.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Commit 69c49382 ("drm/nouveau/instmem/gk20a: use direct CPU access")
tried to be smart while using the DMA-API by managing the CPU mappings of
buffers allocated with the DMA-API by itself. In doing so, it relied
on dma_to_phys() which is an architecture-private function not
available everywhere. This broke the build on several architectures.

Since there is no reliable and portable way to obtain the physical
address of a DMA-API buffer, stop trying to be smart and just use the
CPU mapping that the DMA-API can provide. This means that buffers will
be CPU-mapped for all their life as opposed to when we need them, but
anyway using the DMA-API here is a fallback for when no IOMMU is
available so we should not expect optimal behavior.

This makes the IOMMU and DMA-API implementations of instmem diverge
enough that we should maybe put them into separate files...
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

The LRU list used for recycling CPU mappings was handling concurrency
very poorly. For instance, if an instobj was acquired twice before being
released once, it would end up into the LRU list even though there is
still a client accessing it.

This patch fixes this by properly counting how many clients are
currently using a given instobj.

While at it, we also raise errors when inconsistencies are detected, and
factorize some code.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This is an oversight that made use of the trip-point-based fan managenent on
cards that never expose those. This led the fan to stay at fan_min.

Fortunately, the emergency code would kick when the temperature would reach
90°C.
Reported-by: NTom Englund <tomenglund26@gmail.com>
Tested-by: NTom Englund <tomenglund26@gmail.com>
Signed-off-by: NMartin Peres <martin.peres@free.fr>
Tested-by: NDaemon32 <lnf.purple@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92126Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org

NVIDIA have indicated that the workaround is required on all GK10[467]
boards that have the PGOB fuse set.

I've left the commandline option in place for now, as paranoia.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Reported-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NMartin Peres <martin.peres@free.fr>

No locking is required for the traversal of this list, as it only
happens during suspend/resume where nothing else can be executing.

Fixes some of the issues noticed during parallel piglit runs.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

do_div() must only be used with a u64 dividend.
Signed-off-by: NNicolas Pitre <nico@linaro.org>

gk20a is an ARM only GPU, so we can just do the correct thing on
ARM but fail on other architectures. The other option was to use
SWIOTLB as the define, which means phys_to_page exists, but
this seems clearer.
Signed-off-by: NDave Airlie <airlied@redhat.com>

This patch uses an approach closer to the nvidia driver to configure
both PLLs for high gddr5 memory clocks (usually above 2400MHz)

Previously nouveau used the one PLL as it was used for the lower clocks
and just adjusted the second PLL to get as close as possible to the
requested clock.  This means for my card, that I got a 4050 MHz clock
although 4008 MHz was requested.

Now the driver iterates over a list of PLL configuration also used by
the nvidia driver and then adjust the second PLL to get near the
requested clock.  Also it hold to some restriction I found while
analyzing the PLL configurations

This won't fix all gddr5 high clock issues itself, but it should be
fine on hybrid gpu systems as found on many laptops these days.  Also
switching while normal desktop usage should be a lot more stable than
before.

v2: move the pll code into ramgk104
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Your milage may vary, as it's only been tested on a single G94 and one G96.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Avoids waiting for VBLANKS that never arrive on headless or otherwise
unconventional set-ups. Strategy taken from MEMX.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

10053c is not even read on some cards, and I have no idea exactly what the
criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables
all features that are never used. The practical effect should be the same
as this implementation though.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Like Pierre's G94. We might want to structure Kepler similarly in a follow-up.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Does not seem to be necessary for NVA0, hence untested by me.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Seems to be mostly equal to DDR3 on < GT218, should improve stability for
DDR2 reclocks.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

In preparation of changing FBVDDQ, as observed on at least one GDDR3 card.
While at it, adhere to func.log[1] properly for consistency.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

If the hardware supports extended tag field (8-bit ones), then enable it.

This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).

In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.

Fixes: fdo#86537

v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it
v4:
  * Rename `add` argument of nvkm_pci_mask to `value`
  * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
    checks
v5:
  * Rebase code on latest PCI structure
  * Restore PCIe check
  * Fix namings in nvkm_pci_mask
  * Rephrase part of the commit message
Signed-off-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

coverity.com reported that memset was using a buffer of size 0, on
checking the code it turned out that the function was not being used. So
remove it.
Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org>
Reviewed-by: NSamuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Not 100% confirmed, but seems to match from the few boards I've looked
at so far.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>