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  1. 13 5月, 2016 11 次提交
  3. 20 1月, 2016 4 次提交
    • M
      MIPS: Add IEEE Std 754 conformance mode selection · 503943e0
      由 Maciej W. Rozycki 提交于 
      Add an `ieee754=' kernel parameter to control IEEE Std 754 conformance
mode.

Use separate flags copied from the respective CPU feature flags, and
adjusted according to the conformance mode selected, to make binaries
requesting individual NaN encoding modes accepted or rejected as needed.
Update the initial setting for FCSR and, in the full FPU emulation mode,
its read-only mask accordingly.  Accept the mode selection requested for
legacy processors as well.

As with the EF_MIPS_NAN2008 ELF file header flag adjust both ABS2008 and
NAN2008 bits at the same time, to match the choice made for hardware
currently implemented.
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11481/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      503943e0
    • M
      MIPS: Determine the presence of IEEE Std 754-2008 features · 93adeaf6
      由 Maciej W. Rozycki 提交于 
      Determine the presence of and the amount of control available over IEEE
Std 754-2008 features.

In the case of a hardware FPU being used examine the FIR register for
the presence of the HAS2008 bit and then the FCSR register for the
writability of the ABS2008 and NAN2008 bits and the hardwired state of
each of these bits if read-only.  Update the initial FCSR contents used
for threads and the FCSR writability mask accordingly.

For full FPU emulation and MIPS32 or MIPS64 processors make the FCSR
ABS2008 and NAN2008 bits writable.
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11480/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      93adeaf6
    • M
      MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulation · 90d53a91
      由 Maciej W. Rozycki 提交于 
      Implement IEEE Std 754-2008 NaN encoding wired to the state of the
FCSR.NAN2008 bit.  Make the interpretation of the quiet bit in NaN data
as follows:

* in the legacy mode originally defined by the MIPS architecture the
  value of 1 denotes an sNaN whereas the value of 0 denotes a qNaN,

* in the 2008 mode introduced with revision 5 of the MIPS architecture
  the value of 0 denotes an sNaN whereas the value of 1 denotes a qNaN,
  following the definition of the preferred NaN encoding introduced with
  IEEE Std 754-2008.

In the 2008 mode, following the requirement of the said standard, quiet
an sNaN where needed by setting the quiet bit to 1 and leaving all the
NaN payload bits unchanged.

Update format conversion operations according to the rules set by IEEE
Std 754-2008 and the MIPS architecture.  Specifically:

* propagate NaN payload bits through conversions between floating-point
  formats such that as much information as possible is preserved and
  specifically a conversion from a narrower format to a wider format and
  then back to the original format does not change a qNaN payload in any
  way,

* conversions from a floating-point to an integer format where the
  source is a NaN, infinity or a value that would convert to an integer
  outside the range of the result format produce, under the default
  exception handling, the respective values defined by the MIPS
  architecture.

In full FPU emulation set the FIR.HAS2008 bit to 1, however do not make
any further FCSR bits writable.
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11477/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      90d53a91
    • M
      MIPS: Define the legacy-NaN and 2008-NaN features · 9519ef37
      由 Maciej W. Rozycki 提交于 
      Allocate CPU option bits and define macros for the legacy-NaN and
2008-NaN IEEE Std 754 MIPS architecture features.  Unconditionally mark
the legacy-NaN feature as present across hardware and emulated
floating-point configurations.
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11475/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      9519ef37
  5. 11 11月, 2015 1 次提交
  7. 23 9月, 2015 2 次提交
  9. 03 9月, 2015 4 次提交
  11. 26 8月, 2015 5 次提交
  13. 22 6月, 2015 2 次提交
    • J
      MIPS: R12000: Enable branch prediction global history · 8d5ded16
      由 Joshua Kinard 提交于 
      The R12000 added a new feature to enhance branch prediction called
"global history".  Per the Vr10000 Series User Manual (U10278EJ4V0UM),
Coprocessor 0, Diagnostic Register (22):

"""
If bit 26 is set, branch prediction uses all eight bits of the global
history register.  If bit 26 is not set, then bits 25:23 specify a count
of the number of bits of global history to be used. Thus if bits 26:23
are all zero, global history is disabled.

The global history contains a record of the taken/not-taken status of
recently executed branches, and when used is XOR'ed with the PC of a
branch being predicted to produce a hashed value for indexing the BPT.
Some programs with small "working set of conditional branches" benefit
significantly from the use of such hashing, some see slight performance
degradation.
"""

This patch enables global history on R12000 CPUs and up by setting bit
26 in the branch prediction diagnostic register (CP0 $22) to '1'.  Bits
25:23 are left alone so that all eight bits of the global history
register are available for branch prediction.
Signed-off-by: NJoshua Kinard <kumba@gentoo.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      8d5ded16
    • P
      MIPS: ingenic: Add newer vendor IDs · 252617a4
      由 Paul Burton 提交于 
      Ingenic have actually varied the vendor/company ID of the XBurst cores
across their range of SoCs, whilst keeping the product ID & revision
constant... Add definitions for vendor IDs known to be used in some of
Ingenic's newer SoCs, and handle them in the same way as the existing
Ingenic vendor ID from the JZ4740.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Co-authored-by: NPaul Cercueil <paul@crapouillou.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/10128/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      252617a4
  15. 03 6月, 2015 1 次提交
  17. 08 4月, 2015 5 次提交
  19. 01 4月, 2015 1 次提交
  21. 31 3月, 2015 1 次提交
  23. 20 3月, 2015 1 次提交
  25. 20 2月, 2015 1 次提交
  27. 17 2月, 2015 1 次提交
    • M
      MIPS: Add LLB bit and related feature for the Config 5 CP0 register · 5aed9da1
      由 Markos Chandras 提交于 
      The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:

0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:

- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]

This will be used later on to emulate R2 LL/SC instructions.
Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
      5aed9da1