This is used to configure the pins of the sd_emmc_a controller to
which an SDIO module is connected (when available).
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Amlogic reference driver uses the "mc_val" devicetree property to
configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic
values for this configuration.
According to the datasheet the PRG_ETHERNET_ADDR0 register is at address
0xc8834108. However, the reference driver uses 0xc8834540 instead.
According to my tests, the value from the reference driver is correct.

No changes are required to the board dts files because the only
required configuration option is the phy-mode, which had to be
configured correctly before as well.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NJérôme Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

All of these have a Realtek Gbit RGMII PHY.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the NVMEM device node in the DTSI.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
[khilman: dropped driver cleanup hunk]
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the secure monitor node in the Amlogic Meson GXBB DTSI file to
enable it.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add DT nodes for PWMs in EE and AO domains.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Enable the Infrared Remote Controller on boards which have an Infrared
receiver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the Infrared Remote Controller node so boards with an IR
remote can simply enable it.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the AO clock controller node for the AmLogic GXBB SoC.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

With the clock driver upstream, switch to the real clock.
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the SoC-level description of the PCIe controller found on the Marvell
Armada 3700 and enable this PCIe controller on the development board for
this SoC.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Added mdio node for mdio driver.  Also added phy-handle
reference to the ethernet nodes.

Removed unused clock node from storm sgenet1.
Signed-off-by: NIyappan Subramanian <isubramanian@apm.com>
Tested-by: NFushen Chen <fchen@apm.com>
Tested-by: NToan Le <toanle@apm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

We currently define OBJCOPYFLAGS in the top-level arm64 Makefile, and
thus these flags will be passed to all uses of objcopy, kernel-wide, for
which they are not explicitly overridden. The flags we set are intended
for converting vmlinux (and ELF) into Image (a raw binary), and thus the
flags chosen are problematic for some other uses which do not expect a
raw binary result, e.g. the upcoming lkdtm rodata test:

  http://www.openwall.com/lists/kernel-hardening/2016/06/08/2

This patch localises the objcopy flags such that they are only used for
the vmlinux -> Image conversion.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: NKees Cook <keescook@chromium.org>
Tested-by: NLaura Abbott <labbott@redhat.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

Signed-off-by: NThierry Reding <treding@nvidia.com>

The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA
(super-speed logic), XUSBB (USB device logic) and XUSBC (USB host
logic). Populate the device-tree nodes for these XUSB partitions.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the DPAUX pinctrl states for the DPAUX nodes defining all three
possible states of "aux", "i2c" and "off". Also add the 'i2c-bus'
node for the DPAUX nodes so that the I2C driver core does not attempt
to parse the pinctrl state nodes.

Populate the nodes for the pinctrl clients of the DPAUX pin controller.
There are two clients for each DPAUX instance, namely the SOR and one of
the I2C adapters. The SOR clients may used the DPAUX pins in either AUX
or I2C modes and so for these devices we don't define any of the generic
pinctrl states (default, idle, etc) because the SOR driver will directly
set the state needed. For I2C clients only the I2C mode is used and so
we can simplify matters by using the generic pinctrl states for default
and idle.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the ACONNECT bus node for Tegra210 which is used to interface to
the various devices in the Audio Processing Engine (APE).
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the audio powergate for Tegra210.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add regulators to the Tegra210 Smaug DTS file including support for the
MAX77620 PMIC.
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
the XUSB pad controller. For some Tegra210 boards, this is causing USB
connect and disconnect events to go undetected. Fix this by changing the
interrupt number for the XUSB mailbox to 40.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes
to an internal ethernet interface, while a second USB 3.0 lane supports
the USB-A receptacle on the I/O board.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a chosen node to the device tree that contains a stdout-path
property which defines the debug serial port.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to the USB ports.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a device tree node for the XUSB pad controller found on Tegra210.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel
connected via four DSI lanes.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add power supplies for the SD/MMC card slot. Note that vmmc-supply is
currently restricted to 3.3 V because we don't support switching the
mode yet.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add a device tree node for the MAX77620 PMIC found on the p2180
processor module (Jetson TX1). Also add supporting power supplies,
such as the main 5 V system supply.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add video encoder node for MT8173
Signed-off-by: NTiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>

Add VPU drivers for MT8173
Signed-off-by: NAndrew-CT Chen <andrew-ct.chen@mediatek.com>
Signed-off-by: NTiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>

This reverts commit f3abd629, which caused a build regression:

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:48:41: fatal error: dt-bindings/clock/gxbb-clkc.h: No such file or directory

We should apply this patch one merge window later, once the clk branch
is merged as well.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add pl031 rtc0 and rtc1 support to hi6220 dtsi

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
[jstultz: Forward ported and tweaked commit description,
 added rtc1 entry as suggested by Guodong]
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

Enable the Watchdog Timer (WDT) controller on the Renesas Salvator-X
board equipped with an R-Car M3-W (r8a7796) SoC.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a device node for the Watchdog Timer (WDT) controller on the Renesas
R-Car M3-W (r8a7796) SoC.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Hook up all devices that are part of the CPG/MSSR Clock Domain to the
SYSC "always-on" PM Domain, for a more consistent device-power-area
description in DT.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>