- 15 5月, 2014 2 次提交
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由 Tomasz Figa 提交于
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NHyunhee Kim <hyunhee.kim@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NKarol Wrona <k.wrona@samsung.com> Signed-off-by: NYoungJun Cho <yj44.cho@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org>
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由 Rahul Sharma 提交于
Add support for exynos5260 clocks in clock driver. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 13 5月, 2014 1 次提交
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由 Heiko Stuebner 提交于
This driver can handle the clock controllers of the socs mentioned above, as they share a common clock tree with only small differences. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As pll-rate-tables only the 12mhz variants are currently included. The original code was wrongly checking for 169mhz xti values [a 0 to much at the end], so the original 16mhz pll table would have never been included and its values are so obscure that I have no possibility to at least check their sane-ness. When using the formula from the manual the resulting frequency is near the table value but still slightly off. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 09 5月, 2014 1 次提交
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由 Heiko Stuebner 提交于
This adds a driver for controlling the external clock outputs of s3c24xx architectures including the dclk muxes and dividers. The driver at the moment only supports the legacy non-dt boards using these clock outputs. The clock-output control itself is part of the system-controller mainly controlled by the pinctrl drivers. So it should most likely be integrated there for dt platforms. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 15 4月, 2014 2 次提交
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由 Heiko Stuebner 提交于
This driver can handle the clock controller in the s3c2412 soc. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Heiko Stuebner 提交于
The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 17 9月, 2013 1 次提交
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由 Tomasz Figa 提交于
This patch migrates the s3c64xx platform to use the new clock driver using Common Clock Framework. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 06 8月, 2013 1 次提交
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由 Tomasz Figa 提交于
This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 19 6月, 2013 2 次提交
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由 Chander Kashyap 提交于
The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Padmavathi Venna 提交于
Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 25 3月, 2013 5 次提交
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由 Thomas Abraham 提交于
The Exynos5440 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Thomas Abraham 提交于
The Exynos5250 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Thomas Abraham 提交于
The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Thomas Abraham 提交于
There are several types of pll clocks used in Samsung SoC's and these pll clocks can be represented as Samsung specific pll clock types and registered with the common clock framework. Add support for pll35xx, pll36xx, pll45xx, pll46xx and pll2550x clock types and helper functions to register them. Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Thomas Abraham 提交于
All Samsung platforms include different types of clock including fixed-rate, mux, divider and gate clock types. There are typically hundreds of such clocks on each of the Samsung platforms. To enable Samsung platforms to register these clocks using the common clock framework, a bunch of utility functions are introduced here which simplify the clock registration process. The clocks are usually statically instantiated and registered with common clock framework. Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com> Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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