1. 29 11月, 2012 4 次提交
  2. 23 8月, 2012 3 次提交
  3. 24 6月, 2012 1 次提交
  4. 29 5月, 2012 2 次提交
  5. 16 4月, 2012 1 次提交
    • J
      video: exynos_dp: add analog and pll control setting · 8affaf5c
      Jingoo Han 提交于
      This patch adds analog and pll control setting. This control setting
      is used for DP TX PHY block to set the values as below. It is beneficial
      to improve analog characteristics.
       - TX terminal registor is 50 Ohm.
       - Reference clock of PHY is 24 MHz.
       - Power source for TX digital logic is 1.0625 V.
       - Power source for internal clock driver is 1.0625 V.
       - PLL VCO range setting is 600 uA.
       - Power down ring osc is turned off.
       - AUX terminal resistor is 50 Ohm.
       - AUX channel current is 8 mA and multiplied by 2.
       - TX channel output amplitude is 400 mV.
      Signed-off-by: NJingoo Han <jg1.han@samsung.com>
      Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
      8affaf5c
  6. 13 2月, 2012 1 次提交