Move plat/dma.h to plat-omap/dma-omap.h as part of single
zImage work
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Similar to omap1, some of the omap2+ dma channel definitions are
used by some drivers. For moving omap2+ dma channel definitions
to mach-omap2/, the used ones should be defined locally to driver.
Drivers can eliminate it using DT, platform data, or IORESOURCE_DMA
And moving omap2+ DMA channel definitions to mach-omap2
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

As suggested by Andrew Morton:

  This is a pet peeve of mine.  Any time there's a long list of items
  (header file inclusions, kconfig entries, array initalisers, etc) and
  someone wants to add a new item, they *always* go and stick it at the
  end of the list.

  Guys, don't do this.  Either put the new item into a randomly-chosen
  position or, probably better, alphanumerically sort the list.

lets sort all our select statements alphanumerically.  This commit was
created by the following perl:

while (<>) {
	while (/\\\s*$/) {
		$_ .= <>;
	}
	undef %selects if /^\s*config\s+/;
	if (/^\s+select\s+(\w+).*/) {
		if (defined($selects{$1})) {
			if ($selects{$1} eq $_) {
				print STDERR "Warning: removing duplicated $1 entry\n";
			} else {
				print STDERR "Error: $1 differently selected\n".
					"\tOld: $selects{$1}\n".
					"\tNew: $_\n";
				exit 1;
			}
		}
		$selects{$1} = $_;
		next;
	}
	if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or
			  /^endif/ or /^endchoice/)) {
		foreach $k (sort (keys %selects)) {
			print "$selects{$k}";
		}
		undef %selects;
	}
	print;
}
if (%selects) {
	foreach $k (sort (keys %selects)) {
		print "$selects{$k}";
	}
}

It found two duplicates:

Warning: removing duplicated S5P_SETUP_MIPIPHY entry
Warning: removing duplicated HARDIRQS_SW_RESEND entry

and they are identical duplicates, hence the shrinkage in the diffstat
of two lines.

We have four testers reporting success of this change (Tony, Stephen,
Linus and Sekhar.)
Acked-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Commit eb05f691 ("ARM: OMAP: hwmod:
partially un-reset hwmods might not be properly enabled") added code
to skip the IP block disable sequence if all of the block's hardreset
lines weren't asserted.  But this did not handle the case when no
hardreset lines were associated with a module, which is the general
case.  In that situation, the IP block disable would be skipped.  This
is likely to cause PM regressions.

So, modify _omap4_disable_module() and _am33xx_disable_module() to
only bail out early if there are any hardreset lines asserted.  And
move the AM33xx test above the actual module disable code to ensure
that the behavior is consistent.
Reported-by: NArchit Taneja <a0393947@ti.com>
Tested-by: Archit Taneja <a0393947@ti.com> # DSS
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: NVaibhav Hiremath <hvaibhav@ti.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com> # AM335x
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Commit b71c7217 (ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU
clockdomain idle problems) added a workaround for the EMU clock domain on
OMAP3/4 devices to prevent the clock domain for transitioning while it is
in use.

In the proposed patch [1] code was added to the omap3xxx_clkdm_clk_enable()
and omap3xxx_clkdm_clk_disable() functions to check for the flag
CLKDM_MISSING_IDLE_REPORTING and perform the appropriate action. However, in the
merged patch it appears that this code was added to the omap2_clkdm_clk_enable()
and omap2_clkdm_clk_disable() functions by mistake.

[1] http://marc.info/?l=linux-arm-kernel&m=134383567112518&w=2Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Use the enum for board_ref_clock from linux/wl12xx.h
Signed-off-by: NVikram Narayanan <vikram186@gmail.com>
Cc: linux-omap@vger.kernel.org
Reviewed-by: Pankaj Jangra<jangra.pankaj9@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Remove duplicated include.

dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Found by http://coccinelle.lip6.fr/Signed-off-by: NPeter Senna Tschudin <peter.senna@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

u-boot stopped configuring 'non essential' pins recently. These pins are
essential for audio and need to be done to have working audio on the board.
Pin Mux configuration for: twl6040 audpwron gpio, McPDM, and McBSP1.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

u-boot stopped configuring 'non essential' pins recently. These pins are
essential for audio and need to be done to have working audio on the board.
Pin Mux configuration for: twl6040 audpwron gpio, McPDM, DMIC, McBSP1 and
McBSP2.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch adds a missing hwmod entry for the HDQ/1-Wire module present
in the AM3505/17 CPUs.

This restores 1-Wire support to our AM3505 boards. We think it probably
stopped working with commit 96b1b29d
ARM: OMAP2+: HDQ1W: use omap_device
Signed-off-by: NRaphael Assenat <raph@8d.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

compiler complained,
`gpmc_remove' referenced in section `.data' of arch/arm/mach-omap2/built-in.o: defined in discarded section `.exit.text' of arch/arm/mach-omap2/built-in.o

Annotate gpmc_remove function and dependents with __devexit.
Reported-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

In case of error, the function clk_get() returns ERR_PTR()
and never returns NULL. The NULL test in the return value
check should be replaced with IS_ERR().

dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NTony Lindgren <tony@atomide.com>

In case of error, the function omap_device_alloc() returns ERR_PTR()
not NULL pointer. The NULL test in the return value check should
be replaced with IS_ERR().

dpatch engine is used to auto generated this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NTony Lindgren <tony@atomide.com>

In case of error, the function omap_device_alloc() returns ERR_PTR()
not NULL pointer. The NULL test in the return value check should
be replaced with IS_ERR().

dpatch engine is used to auto generated this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Currently, a dummy omap_device is created for the MPU sub-system so
that a device node exists for MPU DVFS.  Specifically, for the
association of MPU OPPs to a device node, and so that a voltage
regulator can be mapped to a device node.

For drivers to get a handle to this device node, an OMAP-specific API
has been used.  However, the kernel already has device nodes for the
CPU(s) in the system, so we can use those instead of an OMAP-specific
dummy device and then drivers (like OMAP CPUfreq) can use generic
APIs.

To use the existing CPU device nodes, modify the OPP creation and
regulator registration to use the CPU0 device node for registraion.

NOTE: this patch always uses CPU0 as the device node.  On all
      OMAPs today, MPU DVFS scales all CPUs together, so this will
      not be a problem, but this assumption will need to be changed
      if independently scalable CPUs are introduced.

Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

rx51_si4713_dev is referenced only from rx51_init_si4713.
So the memory for rx51_si4713_dev can be safely freed after init.
Also it references rx51_si4713_board_info which is __initdata_or_module.

fixes the below warning.

WARNING: vmlinux.o(.data+0x30958): Section mismatch in reference from the variable rx51_si4713_dev to the (unknown reference) .init.data:(unknown)
The variable rx51_si4713_dev references
the (unknown reference) __initdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Reported-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NShubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

memblock_steal tries to reserve physical memory during boot.
When the requested size is not aligned on the section size
then, the remaining memory available for lowmem becomes
unaligned on the section boundary. There is a issue with this,
which is discussed in the thread below.

https://lkml.org/lkml/2012/6/28/112

The final conclusion from the thread seems to
be align the memblock_steal calls on the SECTION boundary.
The issue comes out when LPAE is enabled, where the
section size is 2MB.

Boot tested this on OMAP5 evm with and without LPAE.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Commit e54adb1e ("ARM: OMAP: omap3evm:
cleanup revision bits") adds a new sparse[1] warning:

arch/arm/mach-omap2/board-omap3evm.c:90:4: warning: symbol 'get_omap3_evm_rev' was not declared. Should it be static?

This symbol no longer appears to be used outside this file, so mark it
static and remove the export.

...

1. https://sparse.wiki.kernel.org/index.php/Main_PageSigned-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tony Lindgren <tony@atomide.com>

Commit 7d7e1eba (ARM: OMAP2+: Prepare for irqs.h removal) and commit ec2c0825
(ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ) updated the way
interrupts for OMAP2/3 devices are defined in the HWMOD data structures to
being an index plus a fixed offset (defined by OMAP_INTC_START). The definition
of the PMU interrupts on OMAP2/3 devices is missing the OMAP_INTC_START offset
and so this is causing the allocation of PMU interrupts to fail on OMAP2/3
devices. So add the offset to fix this.

This is patch is based upon Tony's master branch for OMAP.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

After Rajendra's common-clock preparation series,
commit (a1978ef4da1 - ARM: omap: hwmod: get rid of
all omap_clk_get_by_name usage) the clkdev table need to
update with an entry for clocks used by hwmod to have
clock name same as the alias.

Without this, the clk_get() in omap_hwmod would fail.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Signed-off-by: NAndi Kleen <ak@linux.intel.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

In case of error, the function voltdm_lookup() returns NULL
not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.

dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: NJean Pihet <j-pihet@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

In case of error, the function voltdm_lookup() returns NULL
not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.

dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: NJean Pihet <j-pihet@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

In case of error, the function omap_device_get_by_hwmod_name()
returns ERR_PTR() not NULL pointer. The NULL test in the return
value check should be replaced with IS_ERR().

dpatch engine is used to auto generated this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NKevin Hilman <khilman@ti.com>

On OMAP4 the i2c1 bus is dedicated for the PMIC and audio related devices.
Manufacturers can opt to use different codec than twl6040 and also can add
audio related IC to the bus (external amplifier for example on SDP4430).

Make it possible to add different set of additional devices to i2c1 bus on
OMAP4 boards.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for removal of irqs.h]
Signed-off-by: NTony Lindgren <tony@atomide.com>

OMAP4460 and OMAP4470 devices have dedicated PMU interrupts and so add these
interrupts to the MPU HWMOD so we can use these for PMU events on these
devices. The PMU interrupts need to be the first interrupts in the array of
interrupts as the ARM PMU driver assumes this.

By using these dedicated interrupts we only need to enable the MPU and DEBUG
sub-systems for PMU to work. This is different to OMAP4430 that did not have
dedicated interrupts and required other power domains in addition to the DEBUG
sub-system to be enabled so we could route the PMU events to the CTI interrupts.
Hence, OMAP4460 and OMAP4470 devices can use the same list of HWMODs to create
the PMU device that is using by OMAP3.

Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The original implementation of this patch was done by Ming Lei for PMU on OMAP4
[1]. Since then the PM runtime calls have been moved into the ARM PMU code and
this greatly simplifies the changes.

The another differnce since the original version, is that it is no longer
necessary to call pm_runtime_get/put during the PMU initialisation was we are no
longer accessing the hardware at this stage.

By adding runtime PM support, we can ensure that the appropriate power and clock
domains are kept on while PMU is being used.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074153.html

Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

For OMAP4430 PMU events are routed to the CPU via the cross trigger interface
(CTI) because there are no dedicated interrupts. In order to route the PMU
events via the CTI IRQs, the following modules must be enabled:

        l3_instr, l3_main_3, debugss

Therefore, build the arm-pmu device via these three HWMODs.

However, the CTI support for this platform still needs some work.  Until
that's finished, temporarily disable the PMU on OMAP4430.

Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NMing Lei <ming.lei@canonical.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: temporarily disabled OMAP4430 PMU support until a
 better CTI interface can be implemented; added patch description note]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Convert OMAP2/3 devices to use HWMOD for creating a PMU device. To support PMU
on OMAP2 devices we only need to use MPU sub-system and so we can simply use
the MPU HWMOD to create the PMU device. To support PMU on OMAP3 devices, we need
to use the MPU and DEBUG sub-systems and so use these HWMODs to create the PMU
device for OMAP3.

The MPU HWMOD for OMAP2/3 devices is currently missing the PMU interrupt and so
add the PMU interrupt to the MPU HWMOD for these devices.

This change also moves the PMU code out of the mach-omap2/devices.c files into
its own pmu.c file as suggested by Kevin Hilman to de-clutter devices.c.

Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: fixed checkpatch messages; updated to apply; dropped old-style
 initial filename line in header comments]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

To enable PMU with runtime PM support on OMAP3 devices we need to be able to
dynamically enable and disable the debug sub-system at runtime. By adding HWMOD
data for the debug sub-system for OMAP3, we can build the PMU device using the
debug sub-system HWMOD and control this power domain using runtime PM.
Reviewed-by: NBenoit Cousson <b-cousson@ti.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply; added L4-EMU address space]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The idle status of the IP blocks and clocks inside the EMU clockdomain
isn't taken into account by the PRCM hardware when deciding whether
the clockdomain is idle.  Add a workaround flag in the clockdomain
code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
the code necessary to support it.

If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
clockdomain will be forced active whenever an IP block inside that
clockdomain is in use, even if the clockdomain supports
hardware-supervised idle.  When the kernel indicates that the last
active IP block inside the clockdomain is no longer used, the
clockdomain will be forced idle, or, if that mode is not supported in
the hardware, it will be placed into hardware-supervised idle.

This patch is an equal collaboration with Jon Hunter
<jon-hunter@ti.com>.  Ming Lei <ming.lei@canonical.com>, Will Deacon
<will.deacon@arm.com>, Madhav Vij <mvij@ti.com>, Kevin Hilman
<khilman@ti.com>, Benoît Cousson <b-cousson@ti.com>, and Santosh
Shilimkar <santosh.shilimkar@ti.com> all made essential contributions
to the understanding of EMU clockdomain power management on OMAP.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Madhav Vij <mvij@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NJon Hunter <jon-hunter@ti.com>

Some instances of the DMTIMER peripheral on OMAP devices have the ability
to interrupt the on-chip DSP in addition to the ARM CPU. Add a DMTIMER
attribute to indicate which timers can interrupt the DSP. By using the
omap_dm_timer_request_by_cap() API, driver will now be able to allocate
a DMTIMER that can interrupt the DSP based upon this attribute and not require
the driver to know which instance has this capability.

DMTIMERs that have the ability to interrupt the DSP on OMAP devices are as
follows ...

- OMAP1 (OMAP5912/16xx/17xx) devices	- All 8 DMTIMERs
- OMAP2/3/4 devices			- DMTIMERs 5-8

Please note that for OMAP3+, timer8 has the ability to interrupt the DSP and
generate a PWM output.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Move the OMAP1-specific RNG device creation off to mach-omap1/devices.c,
and create a omap_device-backed registration function for OMAP2+ devices
in mach-omap2/devices.c.

As a nice side-benefit, we can also get rid of
arch/arm/plat-omap/devices.c, thanks to some recent changes from Tony.

One change from the previous behavior is that the RNG devices are now
registered unconditionally.  This should allow the RNG drivers to be
loaded as modules, even if the original kernel was not built that way.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add integration data for the hardware random number generator IP block
on some OMAP SoCs.  This appears to be present on at least OMAP2xxx
and OMAP3xxx SoCs, although it is not so easy to tell.  It may also be
present on other OMAP2+ SoCs.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Create a minimal driver out of gpmc code.  Responsibilities handled by
earlier gpmc initialization is now achieved in probe.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Reviewed-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: fixed some checkpatch messages]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Create API for platforms to adapt GPMC to HWMOD
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Reviewed-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add gpmc hwmod and associated interconnect data
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
[paul@pwsan.com: added comments to the use of HWMOD_INIT_NO_RESET]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add mmu hwmod data for ipu and dsp.

Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: NOmar Ramirez Luna <omar.luna@linaro.org>
Acked-by: NBenoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: cleaned up whitespace]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add mmu hwmod data for iva and isp.

Due to compatibility an ifdef CONFIG_OMAP_IOMMU_IVA2 needs to be
propagated (previously on iommu resource info) to hwmod data in OMAP3,
so users of iommu and tidspbridge can avoid issues of two modules
managing mmu data/irqs/resets; this until tidspbridge can be migrated
to iommu framework.

Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: NOmar Ramirez Luna <omar.luna@linaro.org>
[paul@pwsan.com: fixed some kerneldoc and whitespace; ISP MMUs not present
 on AM35xx so restricted these hwmods to 34xx/36xx]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>