1. 12 2月, 2013 1 次提交
  2. 14 12月, 2012 1 次提交
    • M
      microblaze: Add static qualifiers · c0d997fb
      Michal Simek 提交于
      Adding static to internal variables and functions.
      
      Sparse warnings:
      arch/microblaze/kernel/prom.c:55:6: warning:
      	symbol 'stdout' was not declared. Should it be static?
      arch/microblaze/kernel/prom.c:57:12: warning:
      	symbol 'early_init_dt_scan_chosen_serial' was not declared. Should it be static?
        CC      arch/microblaze/kernel/prom.o
      arch/microblaze/kernel/intc.c:102:5: warning:
      	symbol 'xintc_map' was not declared. Should it be static?
        CC      arch/microblaze/kernel/intc.o
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      c0d997fb
  3. 13 12月, 2012 1 次提交
    • M
      microblaze: Fix intc_enable_or_unmask function · 7958a689
      Michal Simek 提交于
      Intc_enable_or_unmask() is called at the last stage of handle_level_irq().
      
      This function enables the irq first (Write INTC.SIE) and clear ISR next (Write INTC.IAR).
      This would create problems that processor will get into a new interrupt as soon as SIE
      is written because the previous level interrupt has been captured by INTC.
      
      If the description bring some puzzles, here is the details of how interrupt is handled
      for MicroBlaze after Interrupt signal is detected:
      1. disable INTC (INTC.CIE = 1)
      2. Acknowledge INTC (INTC.IAR = 1)
      3. gets into interrupt source's handler, for example, timer's handler
      4. Timer is interrupt handler acknowledge Timer Interrupt Status (Timer.TCSR0[23] = 1), and return
      5. Enable INTC (INTC.SIE = 1)
      6. Acknowledge INTC (INTC.IAR = 1)
      
      INTC continue to capture source inputs even if INTC is disabled (INTC.IER == 1).
      So between the gap of step 2 and step 3, the level interrupt from source makes INTC captures
      a new interrupt and thus the INTC.ISR = 1 during step 3, 4, and 5.
      When INTC is enabled in step 5, INTC's interrupt output will go high immediately.
      
      In summary, the driver should issue step 6 before step 5.
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      7958a689
  4. 23 3月, 2012 1 次提交
  5. 16 2月, 2012 1 次提交
  6. 05 1月, 2012 3 次提交
  7. 27 7月, 2011 1 次提交
  8. 01 4月, 2011 1 次提交
    • M
      microblaze: Fix level/edge irq sensibility · 56d44801
      Michal Simek 提交于
      Patches:
      "microblaze: Convert to new irq function names"
      sha (4adc192e)
      and
      "microblaze: Use generic show_interrupts()"
      sha(9d61c18b)
      
      should also setup edge/level in irq_set_chip_and_handler_name
      name parameter.
      
      Error log:
      ~ # cat /proc/interrupts
                 CPU0
        2:          2  Xilinx INTC-Xilinx INTC  eth0
        3:          2  Xilinx INTC-Xilinx INTC  eth0
        4:        241  Xilinx INTC-Xilinx INTC  timer
        6:        108  Xilinx INTC-Xilinx INTC  serial
      
      Fixed:
      ~ # cat /proc/interrupts
                 CPU0
        2:          2  Xilinx INTC-level     eth0
        3:          2  Xilinx INTC-level     eth0
        4:        238  Xilinx INTC-edge      timer
        6:        108  Xilinx INTC-level     serial
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      Acked-by: NThomas Gleixner <tglx@linutronix.de>
      
      ---
      
      v2: Fix exchanged edge and level
      56d44801
  9. 29 3月, 2011 1 次提交
  10. 09 3月, 2011 2 次提交
  11. 21 10月, 2010 3 次提交
  12. 14 12月, 2009 1 次提交
  13. 18 8月, 2009 1 次提交
  14. 18 5月, 2009 1 次提交
  15. 27 3月, 2009 1 次提交