1. 27 6月, 2006 1 次提交
  2. 13 1月, 2006 1 次提交
  3. 12 1月, 2006 1 次提交
  4. 15 11月, 2005 1 次提交
    • J
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      Jacob Shin 提交于
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
      This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
      The user may interface through sysfs files in order to change the threshold configuration.
      
      bank%d/error_count - reads current error count, write to clear.
      bank%d/interrupt_enable - set/clear interrupt enable.
      bank%d/threshold_limit - read/write the threshold limit.
      
      APIC vector 0xF9 in hw_irq.h.
      5 software defined bank ids in mce.h.
      new apic.c function to setup threshold apic lvt.
      defaults to interrupt off, count enabled, and threshold limit max.
      sysfs interface created on /sys/devices/system/threshold.
      
      AK: added some ifdefs to make it compile on UP
      Signed-off-by: NJacob Shin <jacob.shin@amd.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      89b831ef
  5. 14 11月, 2005 1 次提交
  6. 31 10月, 2005 1 次提交
  7. 13 9月, 2005 2 次提交
    • A
      [PATCH] x86-64: more gratitious linux/irq.h includes · 9cdd304b
      Al Viro 提交于
      	... and with that all instances in arch/x86_64 are gone.
      Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      9cdd304b
    • A
      [PATCH] x86-64: Make remote TLB flush more scalable · e5bc8b6b
      Andi Kleen 提交于
      Instead of using a global spinlock to protect the state
      of the remote TLB flush use a lock and state for each sending CPU.
      
      To tell the receiver where to look for the state use 8 different
      call vectors.  Each CPU uses a specific vector to trigger flushes on other
      CPUs. Depending on the received vector the target CPUs look into
      the right per cpu variable for the flush data.
      
      When the system has more than 8 CPUs they are hashed to the 8 available
      vectors. The limited global vector space forces us to this right now.
      In future when interrupts are split into per CPU domains this could be
      fixed, at the cost of needing more IPIs in flat mode.
      
      Also some minor cleanup in the smp flush code and remove some outdated
      debug code.
      
      Requires patch to move cpu_possible_map setup earlier.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e5bc8b6b
  8. 26 6月, 2005 1 次提交
  9. 24 6月, 2005 1 次提交
  10. 17 4月, 2005 2 次提交