No content changes.  Move 60xx code to be closer to other 60xx code.

Implement flash reset and PCI reset on 50xx and 60xx.
Implement LED enable on 50xx.

- eliminate a bunch of redundant tests by creating a per-chip-family
  set of hooks, mv_hw_ops
- implement more errata, from newer Marvell GPL'd driver

No content change, just prepping up future mv_hw_ops modularization.

Based largely on the GPL'd Marvell vendor driver.

- clear SError and EDMA irq cause registers, after re-init'ing the phy
- move enums with type suffix 'U' to their own enum

Contributed by Jeroen <dekien@pandora.be>

Signed-off-by: NJames Bottomley <James.Bottomley@SteelEye.com>

Use ata_pad_{alloc,free} in two drivers, to factor out common code.

Add ata_pad_{alloc,free} to two other drivers, which needed the padding
but had not been updated.

A few drivers were not following the standard meme of printing out
their driver name and version at module load time; this is fixed
as well.

The second argument to ata_qc_complete() was being used for two
purposes: communicate the ATA Status register to the completion
function, and indicate an error.  On legacy PCI IDE hardware, the latter
is often implicit in the former.  On more modern hardware, the driver
often completely emulated a Status register value, passing ATA_ERR as an
indication that something went wrong.

Now that previous code changes have eliminated the need to use drv_stat
arg to communicate the ATA Status register value, we can convert it to a
mask of possible error classes.

This will lead to more flexible error handling in the future.

We now depend on ->tf_read() to provide us with the contents
of the Error shadow register.

Enforce access rules where appropriate.

If the compiler is smart enough, this may buy us an optimization or two
as a side effect.

Jeff found an endian bug in the Marvell driver (thanks!).  Here's the
fix for it.
Signed-off-by: NBrett Russ <russb@emc.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>

shuffle ifdef location to fix the following warning:
drivers/scsi/sata_mv.c:471: warning: 'mv_dump_mem' defined but not used

adds helpful function header comments.
Signed-off-by: NBrett Russ <russb@emc.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>

This should fix up lockups that people were seeing due to
improper spinlock placement.  Also, the start/stop DMA routines put
guarded trust in the cached state of DMA.
Signed-off-by: NBrett Russ <russb@emc.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>

This is my libata compatible low level driver for the Marvell SATA
family.  Currently it runs in DMA mode on a 6081 chip.

The 5xxx series parts are not yet DMA capable in this driver because
the registers have differences that haven't been accounted for yet.
Basically, I'm focused on the 6xxx series right now.  I apologize for
those seeing problems on the 5xxx series, I've not had a chance to
look at those problems yet.

For those curious, the previous bug causing the SCSI timeout and
subsequent panics was caused by an improper clear of hc_irq_cause in
mv_host_intr().

This version is running well in my environment (6081 chips,
with/without SW raid1) and is showing equal or better performance
compared to the Marvell driver (mv_sata) in my initial tests (timed
dd's of reads/writes to/from memory/disk).

I still need to look at the causes of occasional problems such as this:

ata11: translating stat 0x35 err 0x00 to sense
ata11: status=0x35 { DeviceFault SeekComplete CorrectedError Error }
SCSI error : <10 0 0 0> return code = 0x8000002
Current sda: sense key Hardware Error
end_request: I/O error, dev sda, sector 3155010

and this, seen at init time:

ATA: abnormal status 0x80 on port 0xE093911C

but they aren't showstoppers.
Signed-off-by: NBrett Russ <russb@emc.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>

* sata_mv: remove pci_intx(), now that the same function is in PCI core
* sata_sis: fix variable initialization bug, trim trailing whitespace

This function will go away when pci_intx() finally makes it
into the core PCI layer.

This is my libata compatible low level driver for the Marvell SATA
family.  Currently it successfully runs in PIO mode on a 6081 chip.
EDMA support is in the works and should be done shortly.  Review,
testing (especially on other flavors of Marvell), comments welcome.
Signed-off-by: NBrett Russ <russb@emc.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>