1. 22 7月, 2018 1 次提交
  2. 16 7月, 2018 1 次提交
  3. 24 5月, 2018 4 次提交
  4. 23 5月, 2018 1 次提交
  5. 11 5月, 2018 1 次提交
  6. 26 4月, 2018 1 次提交
  7. 25 4月, 2018 1 次提交
  8. 19 4月, 2018 1 次提交
    • M
      soc: ti: K2G: enhancement to support QMSS in K2G NAVSS · 350601b4
      Murali Karicheri 提交于
      Navigator Subsystem (NAVSS) available on K2G SoC has a cut down
      version of QMSS with less number of queues, internal linking ram
      with lesser number of buffers etc.  It doesn't have status and
      explicit push register space as in QMSS available on other K2 SoCs.
      So define reg indices specific to QMSS on K2G. This patch introduces
      "ti,66ak2g-navss-qm" compatibility to identify QMSS on K2G NAVSS
      and to customize the dts handling code. Per Device manual,
      descriptors with index less than or equal to regions0_size is in region 0
      in the case of K2 QMSS where as for QMSS on K2G, descriptors with index
      less than regions0_size is in region 0. So update the size accordingly in
      the regions0_size bits of the linking ram size 0 register.
      Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
      Signed-off-by: NWingMan Kwok <w-kwok2@ti.com>
      Reviewed-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      350601b4
  9. 14 3月, 2018 1 次提交
  10. 12 3月, 2018 1 次提交
  11. 08 1月, 2018 1 次提交
  12. 21 12月, 2017 2 次提交
  13. 07 12月, 2017 1 次提交
  14. 10 11月, 2017 1 次提交
  15. 31 10月, 2017 1 次提交
  16. 20 10月, 2017 1 次提交
  17. 07 10月, 2017 1 次提交
  18. 23 9月, 2017 1 次提交
  19. 05 9月, 2017 1 次提交
  20. 02 9月, 2017 1 次提交
  21. 23 8月, 2017 1 次提交
  22. 14 8月, 2017 1 次提交
  23. 22 7月, 2017 1 次提交
  24. 21 7月, 2017 1 次提交
  25. 31 5月, 2017 1 次提交
  26. 15 5月, 2017 1 次提交
  27. 03 5月, 2017 1 次提交
    • C
      powerpc/8xx: Adding support of IRQ in MPC8xx GPIO · 726bd223
      Christophe Leroy 提交于
      This patch allows the use of IRQ to notify the change of GPIO status
      on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs
      in the Device Tree.
      
      Ex:
      	CPM1_PIO_C: gpio-controller@960 {
      		#gpio-cells = <2>;
      		compatible = "fsl,cpm1-pario-bank-c";
      		reg = <0x960 0x10>;
      		fsl,cpm1-gpio-irq-mask = <0x0fff>;
      		interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
      		interrupt-parent = <&CPM_PIC>;
      		gpio-controller;
      	};
      
      The property 'fsl,cpm1-gpio-irq-mask' defines which of the 16 GPIOs
      have the associated interrupts defined in the 'interrupts' property.
      Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr>
      Signed-off-by: NScott Wood <oss@buserror.net>
      726bd223
  28. 10 4月, 2017 1 次提交
  29. 04 4月, 2017 2 次提交
  30. 28 2月, 2017 1 次提交
  31. 11 1月, 2017 1 次提交
  32. 10 1月, 2017 1 次提交
  33. 06 1月, 2017 1 次提交
  34. 05 1月, 2017 1 次提交
  35. 09 12月, 2016 1 次提交