In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.

This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
 - Define a parent_map struct to map the relations between PLL source index
 and register configuration value.
 - Add a qcom_find_src_index() function for finding the index of a clock
 matching the specific PLL configuration.
 - Update the {set,get}_parent RCG functions use the newly introduced
 parent_map struct.
 - Convert all existing drivers to the new parent_map tables.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently configure_bank() returns void. Add some error
checking on the regmap calls and propagate if there is
any error.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

According to the common clock framework API, the clk_get_parent() function
should return u8. Currently we are returning negative values on error. Fix
this and use the default parent in case of an error.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Fixes: bcd61c0f (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The ahbix clock can never be turned off in practice. To change the
rates we need to switch the mux off the M/N counter to an always on
source (XO), reprogram the M/N counter to get the rate we want and
finally switch back to the M/N counter. Add a new ops structure
for this type of clock so that we can set the rate properly.

Fixes: c99e515a "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PXO is 25MHz, not 27MHz. Fix the table.

Fixes: 24d8fba4 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NAndy Gross <agross@codeaurora.org>
Tested-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

drivers/clk/qcom/lcc-msm8960.c:577:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: NFengguang Wu <fengguang.wu@intel.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

drivers/clk/qcom/lcc-ipq806x.c:465:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

CC: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NFengguang Wu <fengguang.wu@intel.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

This clock is needed for most audio clock frequencies. Add it.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

regmap_read() returns 0 on success, not the value of the register
that is read. Fix it so we properly detect the frequency plan.

Fixes: b82875ee "clk: qcom: Add MSM8960/APQ8064 LPASS clock
controller (LCC) driver"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

These shifts were copy/pasted from the pcm which is a different
size RCG. Use the correct offsets so that slimbus rates are
correct.

Fixes: b82875ee "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.

Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                        migrated clk-private.h changes to clk.c]

Add an LCC driver for MSM8960/APQ8064 that supports the i2s,
slimbus, and pcm clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NJosh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add support for muxes that use regmap instead of readl/writel
directly. We don't support as many features as clk-mux.c, but
this is good enough to support getting and setting parents.
Adding a table based lookup can be added in the future if needed.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add support for dividers that use regmap instead of readl/writel.
Signed-off-by: NJosh Cartwright <joshc@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Switch to using generic divider code, drop
enable/disable, reword commit text]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

This is in preparation for clock providers to not have to deal with struct clk.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

There is a duplication in a clock name for apq8084 platform that causes
the following warning: "RBCPR_CLK_SRC" redefined

Resolve this by adding a MMSS_ prefix to this clock and making its name
coherent with msm8974 platform.

Fixes: 2b46cd23 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

A platform_driver does not need to set an owner, it will be populated by the
driver core.
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some PLLs may require changing their rate at runtime. Add support
for these PLLs.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the PLL0 that is required for the USB clocks to
work properly.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Fixes: 24d8fba4 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of 256). Replace this entry with 200kHz
which is close enough to 144kHz to be usable.

Cc: Kumar Gala <galak@codeaurora.org>
Cc: Andy Gross <agross@codeaurora.org>
Fixes: 24d8fba4 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some SR type PLLs need to be configured for a certain rate when
linux boots. Add support for these types of PLLs so that we can
program PLL15's rate on apq8064.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the
child of the mdp_src clock. Fix it.

Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.

Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.

Fixes: 49fc825f "clk: qcom: Consolidate common probe code"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Clocks that don't have a pre-divider don't list any pre-divider
in their frequency tables, but their tables are initialized using
aggregate initializers. Use tagged initializers so we properly
assign the m and n values for each frequency. Furthermore, the
mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second
element to pll2 instead of pll8, causing the clock driver to
recalculate the wrong rate for any clocks using this array along
with a rate that uses pll2. Plus the .num_parents field is 3
instead of 4 so you can't even switch the parent to pll3. Finally
I noticed that the jpegd clock improperly indicates that the
pre-divider width is only 2, when it's actually 4 bits wide.

Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Tested-by: NRob Clark <robdclark@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In the case of HDMI clocks, we want to bypass the RCG's ability
to divide the output clock and pass through the parent HDMI PLL
rate. Add a simple set of clk_ops to configure the RCG to do
this. This removes the need to keep adding more frequency entries
to the tv_src clock whenever we want to support a new rate.
Tested-by: NRob Clark <robdclark@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.

This is currently missing clocks for USB HSIC and networking devices.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the multimedia clock controller found on the APQ8084
based platforms. This will allow the multimedia device drivers to
control their clocks.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
[sboyd: Rework parent mapping to avoid conflicts]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the necessary clocks for SATA, PCIe and UFS to the
APQ8084 global clock controller (GCC). This will allow
the above device drivers to control their clocks.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds support for the global clock controller found on
the APQ8084 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add in the handful of new clocks and introduce a new reset table
with the few new resets.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are not visible to the sdcc driver.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The HDMI PLL input to the tv mux is supposed to be 3, not 2. Fix
the code so that we can properly select the HDMI PLL.

Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Reported-by: NRob Clark <robdclark@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Not all clocks are implemented but client drivers can still
request them. Currently we will return a NULL pointer to them if
the clock isn't implemented in software but NULL pointers are
valid clock pointers. Return an error pointer so that driver's
don't proceed without a clock they may actually need.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

A new PLL (gpll4) is added on msm8974 PRO devices to support a
faster sdc1 clock rate. Add support for this and the two new sdcc
cal clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>