Checkpatch warns about spacing around the '<<' operator in the Tegra I2C
driver and so fix these by converting the bit definitions that are using
this operator to use the BIT macro.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Checkpatch warns about some lines over 80 characters in the Tegra I2C
driver and so fix these.

While we are at it, prefix the second instance of "STOP condition" in
the comment with a "the".
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Disabling the adapter after each transfer adds additional delays
for each I2C transfer. Even if we don't wait for it to be disabled
anymore, on next transfer we will need to if we have several transfers
in a row.

Now during the transfer init we check if IC_TAR can be changed
dynamically, the status register for no activity and TX buffer being
empty. In this case we don't need to disable it

When a transfer fails the adapter will still be disabled - this is a
conservative approach. When transfers succeed, the adapter is left
enabled and it's configured so to disable interrupts.

Alternating register reads on 2 slaves:
perf stat -r4 chrt -f 10 ./i2c-test /dev/i2c-1 25000 0x40 0x6 0x1e 0x00

Before:
	8.638705161 seconds time elapsed                  ( +-  5.90% )
After:
	7.516821591 seconds time elapsed                  ( +-  0.11% )
Signed-off-by: NLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: NJosé Roberto de Souza <jose.souza@intel.com>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: NChristian Ruppert <christian.ruppert@alitech.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This adapter can be synthesized with dynamic tar update enabled or disabled.
When enabled it is not necessary to disable the adapter to change the slave
address in some situations, which saves some time per transaction.

There is no direct register to know if this feature is enabled but we can do it
indirectly by writing to the 10BIT_ADDR field in IC_CON: this field is
read only when dynamic tar update is enabled.
Signed-off-by: NLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: NJosé Roberto de Souza <jose.souza@intel.com>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: NChristian Ruppert <christian.ruppert@alitech.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

These are used in 2 places and will be needed in more.
Signed-off-by: NLucas De Marchi <lucas.demarchi@intel.com>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: NChristian Ruppert <christian.ruppert@alitech.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

If we aren't going to continue using the controller we can just disable
it instead of waiting for it to complete. The biggest improvement here
is when a I2C transaction is completed and it doesn't block until
the adapter is disabled. When a new transfer is needed we will disable
and wait for its completion.

This way the adapter will continue changing its state in parallel to the
execution of the thread that requested the I2C transaction saving most
of the time 25~250 usec per I2C transaction.

A simple program doing a register read (1 byte write, 1 byte read)
alternating on 2 different slaves repeated 25k times for each and
measurements taken 4 times we get:

perf stat -r4 chrt -f 10 ./i2c-test /dev/i2c-1 25000 0x40 0x6 0x1e 0x00

Before:
	30.879317977 seconds time elapsed                 ( +- 14.83% )
After:
	8.638705161 seconds time elapsed                  ( +-  5.90% )
Signed-off-by: NJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: NLucas De Marchi <lucas.demarchi@intel.com>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: NChristian Ruppert <christian.ruppert@alitech.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Fast mode is the default speed of i2c-designware which can be overridden
by platform data or by "clock-frequency" device property. Even though
the ACPI 5.1 can pass device properties via _DSD method, shipping systems
define the connection speed between I2C host and each slave in their
I2cSerialBus resources. Which means speed is not defined per bus but per
slave.

As there is now support in i2c-core to find the bus speed from ACPI use
that to set up the bus speed prior registering the I2C adapter.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

ACPI 5 specification doesn't have property for the I2C bus speed but
I2cSerialBus resource descriptor which define each controller-slave
connection define the maximum speed supported by that connection.

Thus finding the maximum safe speed for the bus is to walk through all
I2cSerialBus resources that are associated to I2C controller and use the
speed of slowest connection.

Add function i2c_acpi_find_bus_speed() to the i2c-core that adapter
drivers can call prior registering itself to core.

This implies two-step walk through the I2cSerialBus resources: call to
i2c_acpi_find_bus_speed() does the first scan and finds the safe bus
speed that adapter drivers can set up. Adapter driver registration does
the second scan when i2c-core creates the I2C slaves by calling the
i2c_acpi_register_devices(). In that way the bus speed is set in case
slave device probe gets called during registration and does communication.

Previous version commit 55d38d06 ("i2c: core: Add function for finding
the bus speed from ACPI") got reverted due merge conflicts from
commit 525e6fab ("i2c / ACPI: add support for ACPI reconfigure
notifications").

This version is a bit bigger than previous version but is still sharing
the lowest and complicated part of I2cSerialBus lookup routines with the
existing code.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

I2C ACPI enumeration was originally implemented in another module under
drivers/acpi/ but was later moved into i2c-core with added support for
I2C ACPI operation region.

Rename these acpi_i2c_ prefixed functions, structures and defines in
i2c-core to i2c_acpi_ in order to have more consistent name space.

This is updated version from commit a7003b65 ("i2c: core: Cleanup I2C
ACPI namespace") that got reverted due merge conflicts from
commit 525e6fab ("i2c / ACPI: add support for ACPI reconfigure
notifications").
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This patch enabled high speed mode. High speed mode can be turn on by
setting the clk_freq to 3400000. High speed HCNT and LCNT are needed
as there is no default value provided.
Signed-off-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

DW_IC_CON_MASTER, DW_IC_CON_SLAVE_DISABLE and DW_IC_CON_RESTART_EN are
common config that need to be set for i2c designware master. So, configure
it first without having to repeat inside the if else.
Signed-off-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This patch enabled fast mode plus. The fast mode plus and fast speed
share the same HCNT and LCNT register. So, the fast mode plus will only
run when the HCNT and LCNT value is provided. Else, it will run at fast
speed as default.
Signed-off-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

I2C designware controller can run at fast mode plus and high speed. This
patch adds the capability to get the HCNT, LCNT configuration via
FPCN (fast plus) and HSCN (high speed) ACPI method.
Signed-off-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

I2c designware controller operate speed is configured in the register
IC_CON. Previously the operate speed is determined by a local variable
clk_freq. This patch will move the local variable clk_freq into struct
dw_i2c_dev. This change will ease the set and get of the clk_freq.
Signed-off-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The i2c Octeon and ThunderX drivers are maintained by Cavium.
While at it fix the whitespace errors of the next entry.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Acked-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Initialize booleon values with true instead of 1.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Sort include files alphabetically to reduce probability of merge
conflicts.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The register offsets are different between Octeon and ThunderX so move
them into the algorithm struct and get rid of the define.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Add SMBUS alert interrupt support. For now only device tree is
supported for specifying the alert. In case of ACPI an error
is returned.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The ThunderX SOC uses the same i2c block as the Octeon SOC.
The main difference is that on ThunderX the device is a PCI device
so device probing is done via PCI, interrupts are MSI-X. The
clock rates can be set via device tree or ACPI.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Move common functionality into a separate file in preparation of the
re-use from the ThunderX i2c driver.

Functions are slightly re-ordered but no other changes are included.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This is an intermediate commit in preparation of the driver split.
The module rename in this commit will be reverted in the next patch,
this is just done to make the series bisectible.
Signed-off-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

No longer rely on the implicit matching with the i2c device name, use
an explicit compatible string instead.

Keep a direct pointer to the chip description instead of an index into
the chip description array.
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

No longer rely on the implicit matching with the i2c device name, use
an explicit compatible string instead.
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

The i2c mux core can then take appropriate action depending on if it is
used for an actual i2c mux, for a gate or for an arbitrator (the last
is the case for these drivers). This adds support for the new clearer
and more compact devicetree bindings that was added recently.
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

Backwards compatibility is preserved; the subnodes are in practice
optional.

However, the mux core needs to know what subnode it should examine, so add
a couple of new flags for i2c_mux_alloc for this purpose.

The rule is that if the mux core finds a 'reg' property in the appropriate
subnode, e.g. if 'reg' exists in the 'i2c-mux' subnode, then the mux core
will assume that this is an old style entry and not an i2c-mux subnode
(correspondingly for arbitrators and gates with 'i2c-arb' and 'i2c-gate').
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

Fill the gap for this pre-existing driver.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

Handle i2c gates similarly to how i2c arbitrators are handled.
This gets rid of a pointless 'reg' property for i2c gates.

I.e. this new and more compact style

        some-gate {
                i2c-gate {
                        #address-cells = <1>;
                        #size-cells = <0>;

                        some-i2c-device@50 {
                                reg = <0x50>;
                        };
                };
        };

instead of the old

        some-gate {
                #address-cells = <1>;
                #size-cells = <0>;

                i2c@0 {
                        reg = <0>;

                        #address-cells = <1>;
                        #size-cells = <0>;

                        some-i2c-device@50 {
                                reg = <0x50>;
                        };
                };
        };
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

This gets rid of the need for a pointless 'reg' property for i2c
arbitrators.

I.e. this new and more compact style

	some-arbitrator {
		i2c-arb {
			#address-cells = <1>;
			#size-cells = <0>;

			some-i2c-device@50 {
				reg = <0x50>;
			};
		};
	};

instead of the old

	some-arbitrator {
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@0 {
			reg = <0>;

			#address-cells = <1>;
			#size-cells = <0>;

			some-i2c-device@50 {
				reg = <0x50>;
			};
		};
	};
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

Similar to the new optional 'i2c-bus' subnode from Jon Hunter, this
adds an optional 'i2c-mux' subnode, for similar reasons. I.e. it is
bad of the i2c mux core to assume that any subnode of an i2c mux device
is a potential (when the 'reg' property matches) i2c-mux child bus,
given that i2c mux devices might do more than mux i2c traffic.

So, if an 'i2c-mux' subnode is present, dictate that all i2c-mux child
buses exist beneath that subnode.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

This unifies usage with i2c_lock_bus and i2c_unlock_bus, and paves the
way for the next patch which looks a bit saner with this preparatory
work taken care of beforehand.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The at24 driver doesn't check if the chip is functional in its probe
function. This leads to instantiating devices that are not physically
present. For example the cape EEPROMs for BeagleBone Black are defined
in the device tree at four addresses on i2c2, but normally only one of
them is present.

If the userspace doesn't know the location in advance, it will need to
check if reading the nvmem attributes fails to determine which EEPROM
is actually there.

Try to read a single byte in probe() and bail-out with -ENODEV if the
read fails.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The core will do this for us now.
Signed-off-by: NWolfram Sang <wsa-dev@sang-engineering.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The core will do this for us now.
Signed-off-by: NWolfram Sang <wsa-dev@sang-engineering.com>
Reviewed-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: NPeter Korsgaard <peter@korsgaard.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NNeil Horman <nhorman@tuxdriver.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Acked-by: NRay Jui <ray.jui@broadcom.com>
Acked-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Pull two parisc fixes from Helge Deller:
 "The first patch ensures that the high-res cr16 clocksource (which was
  added in kernel 4.7) gets choosen as default clocksource for parisc.

  The second patch moves the #define of EREFUSED down inside errno.h and
  thus unbreaks building the gccgo compiler"

* 'parisc-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: Fix order of EREFUSED define in errno.h
  parisc: Fix automatic selection of cr16 clocksource

This is an entirely new driver instead of yet another set of patches
to sb_edac.c because:

1) Mapping from PCI devices to socket/memory controller is significantly
   different. Skylake scatters devices on a socket across a number of
   PCI buses.
2) There is an extra level of interleaving via the "mcroute" register
   that would be a little messy to squeeze into the old driver.
3) Validation is getting too expensive. Changes to sb_edac need to
   be checked against Sandy Bridge, Ivy Bridge, Haswell, Broadwell and
   Knights Landing.
Acked-by: NAristeu Rozanski <aris@redhat.com>
Acked-by: NBorislav Petkov <bp@suse.de>
Signed-off-by: NTony Luck <tony.luck@intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

When building gccgo in userspace, errno.h gets parsed and the go include file
sysinfo.go is generated.

Since EREFUSED is defined to the same value as ECONNREFUSED, and ECONNREFUSED
is defined later on in errno.h, this leads to go complaining that EREFUSED
isn't defined yet.

Fix this trivial problem by moving the define of EREFUSED down after
ECONNREFUSED in errno.h (and clean up the indenting while touching this line).
Signed-off-by: NHelge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org

Commit 54b66800 (parisc: Add native high-resolution sched_clock()
implementation) added support to use the CPU-internal cr16 counters as reliable
clocksource with the help of HAVE_UNSTABLE_SCHED_CLOCK.

Sadly the commit missed to remove the hack which prevented cr16 to become the
default clocksource even on SMP systems.
Signed-off-by: NHelge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # 4.7+