1. 28 4月, 2016 2 次提交
  2. 26 4月, 2016 1 次提交
  3. 20 4月, 2016 1 次提交
  4. 24 2月, 2016 2 次提交
    • A
      arm64: switch to relative exception tables · 6c94f27a
      Ard Biesheuvel 提交于
      Instead of using absolute addresses for both the exception location
      and the fixup, use offsets relative to the exception table entry values.
      Not only does this cut the size of the exception table in half, it is
      also a prerequisite for KASLR, since absolute exception table entries
      are subject to dynamic relocation, which is incompatible with the sorting
      of the exception table that occurs at build time.
      
      This patch also introduces the _ASM_EXTABLE preprocessor macro (which
      exists on x86 as well) and its _asm_extable assembly counterpart, as
      shorthands to emit exception table entries.
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      6c94f27a
    • A
      arm64: avoid R_AARCH64_ABS64 relocations for Image header fields · 6ad1fe5d
      Ard Biesheuvel 提交于
      Unfortunately, the current way of using the linker to emit build time
      constants into the Image header will no longer work once we switch to
      the use of PIE executables. The reason is that such constants are emitted
      into the binary using R_AARCH64_ABS64 relocations, which are resolved at
      runtime, not at build time, and the places targeted by those relocations
      will contain zeroes before that.
      
      So refactor the endian swapping linker script constant generation code so
      that it emits the upper and lower 32-bit words separately.
      Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      6ad1fe5d
  5. 10 12月, 2015 1 次提交
  6. 12 10月, 2015 1 次提交
  7. 27 7月, 2015 2 次提交
  8. 20 3月, 2015 1 次提交
  9. 23 2月, 2015 1 次提交
  10. 12 5月, 2014 1 次提交
    • W
      arm64: debug: avoid accessing mdscr_el1 on fault paths where possible · 2a283070
      Will Deacon 提交于
      Since mdscr_el1 is part of the debug register group, it is highly likely
      to be trapped by a hypervisor to prevent virtual machines from debugging
      (buggering?) each other. Unfortunately, this absolutely destroys our
      performance, since we access the register on many of our low-level
      fault handling paths to keep track of the various debug state machines.
      
      This patch removes our dependency on mdscr_el1 in the case that debugging
      is not being used. More specifically we:
      
        - Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
          avoid disabling step in the MDSCR when we don't need to.
          MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
          userspace.
      
        - Ensure debug exceptions are re-enabled on *all* exception entry
          paths, even the debug exception handling path (where we re-enable
          exceptions after invoking the handler). Since we can now rely on
          MDSCR_EL1.SS being cleared by the entry code, exception handlers can
          usually enable debug immediately before enabling interrupts.
      
        - Remove all debug exception unmasking from ret_to_user and
          el1_preempt, since we will never get here with debug exceptions
          masked.
      
      This results in a slight change to kernel debug behaviour, where we now
      step into interrupt handlers and data aborts from EL1 when debugging the
      kernel, which is actually a useful thing to do. A side-effect of this is
      that it *does* potentially prevent stepping off {break,watch}points when
      there is a high-frequency interrupt source (e.g. a timer), so a debugger
      would need to use either breakpoints or manually disable interrupts to
      get around this issue.
      
      With this patch applied, guest performance is restored under KVM when
      debug register accesses are trapped (and we get a measurable performance
      increase on the host on Cortex-A57 too).
      
      Cc: Ian Campbell <ian.campbell@citrix.com>
      Tested-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      2a283070
  11. 25 10月, 2013 2 次提交
  12. 18 5月, 2013 1 次提交
  13. 05 12月, 2012 1 次提交
  14. 17 9月, 2012 1 次提交