Upon registering a FPGA Manager low level driver, FPGA Manager
core overwrites the platform drvdata pointer. Prior to this commit
zynq-fpga falsely relied on this pointer to still be valid at remove()
time.
Reported-by: NAlan Tull <atull@opensource.altera.com>
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Acked-by: NAlan Tull <atull@opensource.altera.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This gets rid of the code to strip away the header and byteswap,
as well as the check for the sync word.
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NJosh Cartwright <joshc@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This commit fixes the unbalanced clock handling, where
a failed probe would leave the clock with an enable count of -1.
Reported-by: NJosh Cartwright <joshc@ni.com>
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This commit adds FPGA Manager support for the Xilinx Zynq chip.
The code borrows some from the xdevcfg driver in Xilinx'
vendor tree.
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>