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  1. 05 12月, 2009 4 次提交
  3. 22 9月, 2009 2 次提交
    • M
      ixp4xx: arch_idle() documentation fixup · 74c32e72
      由 Mikael Pettersson 提交于 
      The body of the mach-ixp4xx arch_idle() is mysteriously
disabled by an #if 0 .. #endif. Normally one would expect
to find a call to cpu_do_idle() there, but that call is
disabled, even though cpu_do_idle() is implemented for
XScale cores (and ixp4xx is one).

The explanation can be found in the ixp42x developer's manual
which states that the XScale core clock and power management
registers aren't implemented on ixp42x [3.5.2.2].

Also, the disabled code has suffered from bit rot:
- it checks hlt_counter which is obsolete, as that variable
  and all related code now is private to kernel/process.c
- it passes too many parameters to cpu_do_idle()

So this patch:
- adds a comment before the #if 0 to explain why
  cpu_do_idle() mustn't be called on ixp4xx
- removes the obsolete test of hlt_counter and the
  obsolete parameter to cpu_do_idle()

This is purely a documentation fixup and changes no
generated code. Even so, it has been tested on an
ixp420 machine (ds101).
Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
      74c32e72
    • M
      ixp4xx: timer and clocks cleanups · ceb69a89
      由 Mikael Pettersson 提交于 
      This patch does a few simple cleanups of the ixp4xx timer
and clocksource/clockevent code in mach-ixp4xx/common.c:

- ixp4xx_clocksource_init() is static and always returns 0,
  which is ignored by its only caller: make it return void
- ixp4xx_clockevent_init(): ditto
- ixp4xx_get_cycles() is only referenced locally: make it static
- use the ixp4xx_timer_irq.dev_id field to pass &clockevent_ixp4xx
  to ixp4xx_timer_interrupt() via its dev_id parameter, allowing
  the code in ixp4xx_timer_interrupt() to be smaller and faster

Tested on an ixp420 machine (ds101).
Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
      ceb69a89
  5. 07 9月, 2009 1 次提交
    • K
      IXP42x HSS support for setting internal clock rate · 5dbc4650
      由 Krzysztof Halasa 提交于 
      HSS usually uses external clocks, so it's not a big deal. Internal clock
is used for direct DTE-DTE connections and when the DCE doesn't provide
it's own clock.

This also depends on the oscillator frequency. Intel seems to have
calculated the clock register settings for 33.33 MHz (66.66 MHz timer
base). Their settings seem quite suboptimal both in terms of average
frequency (60 ppm is unacceptable for G.703 applications, their primary
intended usage(?)) and jitter.

Many (most?) platforms use a 33.333 MHz oscillator, a 10 ppm difference
from Intel's base.

Instead of creating static tables, I've created a procedure to program
the HSS clock register. The register consists of 3 parts (A, B, C).
The average frequency (= bit rate) is:
66.66x MHz / (A  + (B + 1) / (C + 1))
The procedure aims at the closest average frequency, possibly at the
cost of increased jitter. Nobody would be able to directly drive an
unbufferred transmitter with a HSS anyway, and the frequency error is
what it really counts.

I've verified the above with an oscilloscope on IXP425. It seems IXP46x
and possibly IXP43x use a bit different clock generation algorithm - it
looks like the avg frequency is:
(on IXP465) 66.66x MHz / (A  + B / (C + 1)).
Also they use much greater precomputed A and B - on IXP425 it would
simply result in more jitter, but I don't know how does it work on
IXP46x (perhaps 3 least significant bits aren't used?).

Anyway it looks that they were aiming for exactly +60 ppm or -60 ppm,
while <1 ppm is typically possible (with a synchronized clock, of
course).

The attached patch makes it possible to set almost any bit rate
(my IXP425 533 MHz quits at > 22 Mb/s if a single port is used, and the
minimum is ca. 65 Kb/s).

This is independent of MVIP (multi-E1/T1 on one HSS) mode.
Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5dbc4650
  7. 12 8月, 2009 1 次提交
    • M
      IXP4xx: Fix IO_SPACE_LIMIT for 2.6.31-rc core PCI changes · dee2b904
      由 Mikael Pettersson 提交于 
      2.6.31-rc kernels don't boot on my ixp4xx box (ds101), because the libata
driver doesn't find the PCI IDE controller any more. 2.6.30 was fine.
I traced this to a PCI update (1f82de10)
in 2.6.30-git19. Diffing the kernel boot logs from 2.6.30-git18 and
2.6.30-git19 illustrates the breakage:

> --- dmesg-2.6.30-git18	2009-08-04 01:45:22.000000000 +0200
> +++ dmesg-2.6.30-git19	2009-08-04 01:45:46.000000000 +0200
> @@ -26,6 +26,13 @@
>  pci 0000:00:02.2: PME# supported from D0 D1 D2 D3hot
>  pci 0000:00:02.2: PME# disabled
>  PCI: bus0: Fast back to back transfers disabled
> +pci 0000:00:01.0: BAR 0: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 1: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 2: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 3: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 4: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:02.0: BAR 4: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:02.1: BAR 4: can't allocate I/O resource [0x10000-0xffff]
>  bio: create slab <bio-0> at 0
>  SCSI subsystem initialized
>  NET: Registered protocol family 2
> @@ -44,11 +51,7 @@
>  console [ttyS0] enabled
>  serial8250.0: ttyS1 at MMIO 0xc8001000 (irq = 13) is a XScale
>  Driver 'sd' needs updating - please use bus_type methods
> -PCI: enabling device 0000:00:01.0 (0140 -> 0141)
> -scsi0 : pata_artop
> -scsi1 : pata_artop
> -ata1: PATA max UDMA/100 cmd 0x1050 ctl 0x1060 bmdma 0x1040 irq 28
> -ata2: PATA max UDMA/100 cmd 0x1058 ctl 0x1064 bmdma 0x1048 irq 28
> +pata_artop 0000:00:01.0: no available native port
>  Using configured DiskOnChip probe address 0x50000000
>  DiskOnChip found at 0x50000000
>  NAND device: Manufacturer ID: 0x98, Chip ID: 0x73 (Toshiba NAND 16MiB 3,3V 8-bit)

The specific change in 1f82de10 responsible
for this failure turned out to be the following:

> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -193,7 +193,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
>  		res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
>  		if (type == pci_bar_io) {
>  			l &= PCI_BASE_ADDRESS_IO_MASK;
> -			mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
> +			mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
>  		} else {
>  			l &= PCI_BASE_ADDRESS_MEM_MASK;
>  			mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

Every arch except arm's ixp4xx defines IO_SPACE_LIMIT as an all-bits-one
bitmask, typically -1UL but sometimes only a 16-bit 0x0000ffff. But ixp4xx
defines it as 0xffff0000, which is now causing the PCI failures.

Russell King noted that ixp4xx has 64KB PCI IO space, so IO_SPACE_LIMIT
should be 0x0000ffff. This patch makes that change, which fixes the PCI
failures on my ixp4xx box.
Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
      dee2b904
  9. 25 5月, 2009 1 次提交
  11. 24 5月, 2009 5 次提交
  13. 20 5月, 2009 1 次提交
  15. 09 5月, 2009 1 次提交
  17. 22 4月, 2009 1 次提交
  19. 20 3月, 2009 1 次提交
    • R
      [ARM] pass reboot command line to arch_reset() · be093beb
      由 Russell King 提交于 
      OMAP wishes to pass state to the boot loader upon reboot in order to
instruct it whether to wait for USB-based reflashing or not.  There is
already a facility to do this via the reboot() syscall, except we ignore
the string passed to machine_restart().

This patch fixes things to pass this string to arch_reset().  This means
that we keep the reboot mode limited to telling the kernel _how_ to
perform the reboot which should be independent of what we request the
boot loader to do.
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      be093beb
  21. 17 3月, 2009 4 次提交
  23. 22 12月, 2008 3 次提交
  25. 13 12月, 2008 1 次提交
  27. 30 11月, 2008 2 次提交
  29. 29 11月, 2008 2 次提交
  31. 28 11月, 2008 1 次提交
    • N
      [ARM] remove a common set of __virt_to_bus definitions · b5ee9002
      由 Nicolas Pitre 提交于 
      Let's provide an overridable default instead of having every machine
class define __virt_to_bus and __bus_to_virt to the same thing.  What
most platforms are using is bus_addr == phys_addr so such is the default.

One exception is ebsa110 which has no DMA what so ever, so the actual
definition is not important except only for proper compilation.  Also
added a comment about the special footbridge bus translation.

Let's also remove comments alluding to set_dma_addr which is not
(and should not) be commonly used.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      b5ee9002
  33. 30 10月, 2008 1 次提交
  35. 28 10月, 2008 1 次提交
  37. 17 10月, 2008 1 次提交
  39. 06 9月, 2008 2 次提交
  41. 01 9月, 2008 1 次提交
  43. 19 8月, 2008 1 次提交
  45. 07 8月, 2008 2 次提交