Most users of IS_ERR_VALUE() in the kernel are wrong, as they
pass an 'int' into a function that takes an 'unsigned long'
argument. This happens to work because the type is sign-extended
on 64-bit architectures before it gets converted into an
unsigned type.

However, anything that passes an 'unsigned short' or 'unsigned int'
argument into IS_ERR_VALUE() is guaranteed to be broken, as are
8-bit integers and types that are wider than 'unsigned long'.

Andrzej Hajda has already fixed a lot of the worst abusers that
were causing actual bugs, but it would be nice to prevent any
users that are not passing 'unsigned long' arguments.

This patch changes all users of IS_ERR_VALUE() that I could find
on 32-bit ARM randconfig builds and x86 allmodconfig. For the
moment, this doesn't change the definition of IS_ERR_VALUE()
because there are probably still architecture specific users
elsewhere.

Almost all the warnings I got are for files that are better off
using 'if (err)' or 'if (err < 0)'.
The only legitimate user I could find that we get a warning for
is the (32-bit only) freescale fman driver, so I did not remove
the IS_ERR_VALUE() there but changed the type to 'unsigned long'.
For 9pfs, I just worked around one user whose calling conventions
are so obscure that I did not dare change the behavior.

I was using this definition for testing:

 #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \
       unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO))

which ends up making all 16-bit or wider types work correctly with
the most plausible interpretation of what IS_ERR_VALUE() was supposed
to return according to its users, but also causes a compile-time
warning for any users that do not pass an 'unsigned long' argument.

I suggested this approach earlier this year, but back then we ended
up deciding to just fix the users that are obviously broken. After
the initial warning that caused me to get involved in the discussion
(fs/gfs2/dir.c) showed up again in the mainline kernel, Linus
asked me to send the whole thing again.

[ Updated the 9p parts as per Al Viro  - Linus ]
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lkml.org/lkml/2016/1/7/363
Link: https://lkml.org/lkml/2016/5/27/486
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The struct irq_domain contains a "struct device_node *" field
(of_node) that is almost the only link between the irqdomain
and the device tree infrastructure.

In order to prepare for the removal of that field, convert all
users to use irq_domain_get_of_node() instead.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Reviewed-and-tested-by: NHanjun Guo <hanjun.guo@linaro.org>
Tested-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Tomasz Nowicki <tomasz.nowicki@linaro.org>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Jake Oshins <jakeo@microsoft.com>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Link: http://lkml.kernel.org/r/1444737105-31573-2-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Link: http://lkml.kernel.org/r/1440889285-5637-3-git-send-email-robh@kernel.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The GIC controller doesn't provides any facility to configure the wakeup
sources. For the same reason, GIC chip implementation can't provide
irq_set_wake functionality, but that results in the irqchip core
preventing the systems from entering sleep states like "suspend to RAM".

The GICv1/v2 controllers support wakeup events. They signal these wakeup
events even when CPU interface is disabled which means the wakeup
outputs are always enabled with the required logic in always-on domain.
An implementation can powerdown the GIC completely, but then the wake-up
must be relayed to some control logic within the power controller that
acts as wake-up interrupt controller.

Setting the IRQCHIP_SKIP_SET_WAKE flags will ensure that the interrupts
from GIC can work as wakeup interrupts and resume from suspend-to-{idle,
ram}. The wakeup interrupt sources need to use enable_irq_wake() and the
irqchip core will then set the IRQD_WAKEUP_STATE flag.

Also it's always safer to mask all the non wakeup interrupts are masked
at the chip level when suspending. The irqchip infrastructure can handle
masking of those interrupts at the chip level. The chip implementation
just have to indicate that with IRQCHIP_MASK_ON_SUSPEND.

This patch enables IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND so
that the irqchip core allows and handles the power managemant wake up
modes.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1436971109-20189-1-git-send-email-sudeep.holla@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so
the local irqchip.h became an empty shell, which solely includes
include/linux/irqchip.h

Include the global header in all irqchip drivers instead of the local
header, so we can remove it.
Signed-off-by: NJoel Porquet <joel@porquet.org>
Cc: vgupta@synopsys.com
Cc: monstr@monstr.eu
Cc: ralf@linux-mips.org
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbookSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

GIC requires to disable the interrupt before changing the trigger type.
irqchip core provides IRQCHIP_SET_TYPE_MASKED flag and ensures that the
interrupt is masked before calling chip.irq_set_type() if the irqchip
sets the flag.

This patch adds IRQCHIP_SET_TYPE_MASKED to GIC irqchip so that the core
can manage disabling the interrupt while changing the trigger type.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1433501997-19205-1-git-send-email-sudeep.holla@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

During a recent cleanup of the arm64 DTs it has become clear that
the handling of PPIs in xxxx_set_type() is incorrect. The ARM TRMs
for GICv2 and later allow for "implementation defined" support for
setting the edge or level type of the PPI interrupts and don't restrict
the activation level of the signal. Current ARM implementations
do restrict the PPI level type to IRQ_TYPE_LEVEL_LOW, but licensees
of the IP can decide to shoot themselves in the foot at any time.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NMarc Zyngier <Marc.Zyngier@arm.com>
Cc: LAKML <linux-arm-kernel@lists.infradead.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Link: http://lkml.kernel.org/r/1421772779-25764-1-git-send-email-Liviu.Dudau@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

HiP04 GIC extends to support 16 cores, so we should
initialize the hip04_cpu_map to 0xffff.
Signed-off-by: NWang Long <long.wanglong@huawei.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Link: https://lkml.kernel.org/r/1418295816-179583-1-git-send-email-long.wanglong@huawei.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The HIP04 GIC-like irqchip escaped the conversion to handle_domain_irq.
Let's give it the treatment it deserves.

Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1413882576-18922-1-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

HiP04 GIC is the variate of ARM GICv2.

ARM GICv2 supports 8 cores. HiP04 GIC extends to support 16 cores. It
results that bit fields in GIC_DIST_TARGET & GIC_DIST_SOFTINT are
different from ARM GICv2. And the maximium IRQ is downgrade from 1020 to 510.

Since different register offset & bitfields definitation breaks
compartible with ARM GICv2, create a new hip04 irq driver.

And this driver is derived from irq-gic.c to support the Hisilicon HiP04
interrupt controller, which is similar to the GIC, but deviates at some
points. Support for power management, non-banked registers, cascaded
GICs (and multiple controllers in general) and bigLittle support has
been removed from the GIC driver.

Affinity related functions have been adjusted to match the Hisilicon
hardware implementation.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Link: https://lkml.kernel.org/r/1407408695-19626-9-git-send-email-haojian.zhuang@linaro.orgSigned-off-by: NJason Cooper <jason@lakedaemon.net>