1. 21 1月, 2010 4 次提交
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  5. 07 1月, 2010 1 次提交
    • B
      ARM: S3C64XX: Fix possible clock look in EPLL and MPLL clock chains · 87d26d2d
      Ben Dooks 提交于
      There is a possibility of a loop happening in the PLL output clock
      chain on the S3C64XX series. clk_mpll's parent was set to be
      clk_mout_mpll, but this is fed from clk_fout_epll (which is also
      clk_mpll).
      
      clk_mpll is meant to be the output from the MPLL, and clk_mout_mpll
      is a seperate clock derived from the mux of clk_mpll and clk_fin_mpll
      and thus should be considered a seperate clock.
      
      Anything using clk_mpll directly really should not be relying on this
      being the clock that is eventually routed to a peripheral, so remove the
      loop and ensure that the clocks accurately represent the clock chain
      in the device.
      
      The clk_mpll is not being used outside of the s3c6400-clock.c code, so
      this change should not break anything else.
      
      Do the same for the EPLL.
      Signed-off-by: NBen Dooks <ben-linux@fluff.org>
      87d26d2d
  6. 04 12月, 2009 2 次提交
  7. 01 12月, 2009 6 次提交
  8. 18 11月, 2009 1 次提交
  9. 10 11月, 2009 4 次提交