- 29 2月, 2012 2 次提交
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由 Alex Deucher 提交于
tidy up the radeon_asic struct, handle multiple rings better. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
So don't confuse devs by doing so. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NAlex Deucher <alex.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 05 1月, 2012 1 次提交
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由 Jerome Glisse 提交于
This avoid to waste ib pool size and avoid a bunch of wait for previous ib to finish. Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 21 12月, 2011 11 次提交
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由 Jerome Glisse 提交于
Somewhat specializaed sub-allocator designed to perform sub-allocation for command buffer not only for current cs ioctl but for future command submission ioctl as well. Patch also convert current ib pool to use the sub allocator. Idea is that ib poll buffer can be share with other command buffer submission not having 64K granularity. v2 Harmonize pool handling and add suspend/resume callback to pin/unpin sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman, rs480, rs690, rs880) v3 Simplify allocator v4 Fix radeon_ib_get error path to properly free fence Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NChristian König <deathsimple@vodafone.de> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Some rptr/wptrs fields have different offsets and not all rings are pm4 so add a new nop field. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NChristian König <deathsimple@vodafone.de> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Jerome Glisse 提交于
Add a start fence driver helper function which will be call once for each ring and will compute cpu/gpu addr for fence depending on wether to use wb buffer or scratch reg. This patch replace initialize fence driver separately which was broken in regard of GPU lockup. The fence list for created, emited, signaled must be initialize once and only from the asic init callback not from the startup call back which is call from the gpu reset. v2: With this in place we no longer need to know the number of rings in fence_driver_init, also writing to the scratch reg before knowing its offset is a bad idea. v3: rebase on top of change to previous patch in the serie Signed-off-by: NChristian König <deathsimple@vodafone.de> Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
Those debugfs files aren't r600 specific, so they shouldn't be in r600.c. Move them to radeon_ring.c and also add functionality to dump CP1 & CP2 ring informations. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
That naming seems to make more sense, since we not only want to run PM4 rings with it. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
Replace cp, cp1 and cp2 members with just an array of radeon_cp structs. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
Every ring seems to have the concept of read and write pointers. Make the register offset variable so we can use the functions for different types of rings. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
Give all asic and radeon_ring_* functions a radeon_cp parameter, so they know the ring to work with. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
They are used to sync between rings, while fences sync between a ring and the cpu. v2 Fix radeon_semaphore_driver_fini when no semaphore were allocated. v3 Initialize list early on to avoid issue in case or early error Signed-off-by: NChristian König <deathsimple@vodafone.de> Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
For supporting multiple CP ring buffers, async DMA engines and UVD. We still need a way to synchronize between engines. v2 initialize unused fence driver ring to avoid issue in suspend/unload Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 11 11月, 2011 2 次提交
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由 Alex Deucher 提交于
Avoid a lot of extra loops through the pm state array. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
The new power tables need to be handled differently when setting up the profiles. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 04 11月, 2011 2 次提交
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由 Jerome Glisse 提交于
After GPU lockup VRAM gart table is unpinned and thus its pointer becomes unvalid. This patch move the unpin code to a common helper function and set pointer to NULL so that page update code can check if it should update GPU page table or not. That way bo still bound to GART can be unbound (pci_unmap_page for all there page) properly while there is no need to update the GPU page table. V2 move the test for null gart out of the loop, small optimization Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Polarity needs to be set accordingly to connector status (connected or disconnected). Set it up in hpd_init() so first hotplug works reliably no matter what is the initial set of connector. hpd_init() also covers resume so HPD will work correctly after resume as well. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: Jerome Glisse <j.glisse@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 11月, 2011 2 次提交
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由 Alex Deucher 提交于
The vram scratch was originally only used on some 7xx asics to work around a hw bug. Allocate the scratch page on all 6xx+ radeons and set the MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR to point to it. We shouldn't ever hit it since we limit the system aperture to vram or vram and AGP, but better safe than sorry. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Jerome Glisse 提交于
Cayman seems to be particularly sensitive to read cache returning old data after bind/unbind to GTT. Flush read cache for GTT range with each fences for all new hw. Should fix several rendering glitches. Like V2 flush whole address space V3 also flush shader read cache https://bugs.freedesktop.org/show_bug.cgi?id=40221 https://bugs.freedesktop.org/show_bug.cgi?id=38022 https://bugzilla.redhat.com/show_bug.cgi?id=738790Signed-off-by: NJerome Glisse <jglisse@redhat.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 01 11月, 2011 1 次提交
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由 Paul Gortmaker 提交于
So that we don't get build failures once the implicit module.h presence is removed. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
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- 18 10月, 2011 3 次提交
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由 Alex Deucher 提交于
r600-NI shared the same blit suspend code. Clean it up and make it a shared function. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Covert 4k pages to multiples of 64x64x4 tiles. This is also more efficient than a scanline based approach from the MC's perspective. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Andi Kleen 提交于
With this patch I'm only about 50k larger with DRM debugging enables (why is that enabled by default?!?), and slightly smaller without. [airlied: moved r100.c additions to radeon_ring.c] Signed-off-by: NAndi Kleen <ak@linux.intel.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 19 9月, 2011 1 次提交
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由 Alex Deucher 提交于
The BO blit code inconsistenly handled the page size. This wasn't an issue on system with 4k pages since the GPU's page size is 4k as well. Switch the driver blit callbacks to take num pages in GPU page units. Fixes lemote mipsel systems using AMD rs780/rs880 chipsets. v2: incorporate suggestions from Michel. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 14 9月, 2011 1 次提交
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由 Michel Dänzer 提交于
Apparently this doesn't always work reliably, e.g. at resume time. Just initialize to 0, so the ring is considered empty. Tested with hibernation on Sumo and Cayman cards. Should fix https://bugs.launchpad.net/ubuntu/+source/linux/+bug/820746/ . Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 06 9月, 2011 1 次提交
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由 Tormod Volden 提交于
This was previously done for r300 only. Use %016llX instead of %08X for printing the table address. Also fix typos in gart warning messages. Signed-off-by: NTormod Volden <debian.tormod@gmail.com> Reviewed-by: NMichel Dänzer <michel@daenzer.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 25 7月, 2011 3 次提交
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由 Benjamin Herrenschmidt 提交于
We should have a read memory barrier between reading the WPTR from memory and reading ring entries based on that value (ie, we need to ensure both loads are done in order by the CPU). It could be argued that the MMIO reads in r600_ack_irq() might be enough to get that barrier but I prefer keeping an explicit one just in case. [airlied: fix evergreen + r/w mixup] Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMatt Turner <mattst88@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Benjamin Herrenschmidt 提交于
When not using MSIs, there is no guarantee that DMA from the device has been fully flushed to point where it's visible to the CPU when taking an interrupt. To get this guarantee, we need to perform an MMIO read from the device, which will flush all outstanding DMAs from bridges between the device and the system. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Benjamin Herrenschmidt 提交于
The writeback ring pointer and IH ring pointer are read using le32_to_cpu so we do not want the chip to byteswap them on big-endian. We still want to byteswap the ring itself and the IBs, so we don't touch that but we remove setting of the byteswap bits in CP_RB_RPTR_ADDR and IH_CNTL. In general, for things like that where we control all the accessors easily, we are better off doing the swap in SW rather than HW. Paradoxally, it does keep the code closer to x86 and avoid using poorly tested HW features. I also changed the use of RADEON_ to R600_ in a couple of cases to be more consistent with the surrounding code. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NMichel Dänzer <michel@daenzer.net> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 7月, 2011 1 次提交
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由 Alex Deucher 提交于
The 3D driver need to get the pipe to backend map to certain things. Add a query to get the info. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 07 7月, 2011 1 次提交
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由 Jerome Glisse 提交于
ib pool weren't free for various newer asic on module unload. This doesn't cause much arm but still could be candidate for stable. Signed-off-by: NJerome Glisse <jglisse@redhat.com> cc: stable@kernel.org Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 21 6月, 2011 1 次提交
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由 Alex Deucher 提交于
0xff01 is not an actual voltage value, but a flag for the driver. If the power state as that value, skip setting the voltage. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 20 6月, 2011 1 次提交
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由 Dave Airlie 提交于
Since we were calling the wptr function before checking if the IH was even enabled, or the GPU wasn't shutdown, we'd get spam in the logs when the GPU readback 0xffffffff. This reorders things so we return early in the no IH and GPU shutdown cases. Reported-and-tested-by: ManDay on #radeon Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 09 6月, 2011 1 次提交
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由 Ilija Hadzic 提交于
debug statement for GUI idle interrupt is wrong and incorrectly reports CP EOP interrupt; trivial issue, but confusing for someone trying to distinguish interrupt sources while debugging ... fixed Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 6月, 2011 1 次提交
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由 Alex Deucher 提交于
- add gpu init support - add blit support - add ucode loader Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 20 4月, 2011 1 次提交
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由 Cédric Cano 提交于
agd5f: fix commit message. Signed-off-by: NCedric Cano <ccano@interfaceconcept.com> Reviewed-by: NMichel Dänzer <michel@daenzer.net> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 13 4月, 2011 2 次提交
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由 Alex Deucher 提交于
This is needed for setting voltages other than vddc. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
As per Konrad's original patch, the dummy page used by the gart code and allocated in radeon_gart_init() was not freed properly in radeon_gart_fini(). At the same time r6xx and newer allocated and freed the dummy page on their own. So to do Konrad's patch one better, just remove the allocation and freeing of the dummy page in the r6xx, 7xx, evergreen, and ni code and allocate and free in the gart_init/fini() functions for all asics. Cc: Jerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Acked-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 14 3月, 2011 1 次提交
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由 Dave Airlie 提交于
So we used to use lpfn directly to restrict VRAM when we couldn't access the unmappable area, however this was removed in 93225b0d as it also restricted the gtt placements. However it was only later noticed that this broke on some hw. This removes the active_vram_size, and just explicitly sets it when it changes, TTM/drm_mm will always use the real_vram_size, and the active vram size will change the TTM size used for lpfn setting. We should re-work the fpfn/lpfn to per-placement at some point I suspect, but that is too late for this kernel. Hopefully this addresses: https://bugs.freedesktop.org/show_bug.cgi?id=35254 v2: fix reported useful VRAM size to userspace to be correct. Signed-off-by: NDave Airlie <airlied@redhat.com>
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