1. 16 5月, 2008 1 次提交
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    • T
      jmicron: update quirk for JMB361/3/5/6 · 3a9e3a51
      Tejun Heo 提交于
      Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the
      quirk.  This has the following effects and is recommended by the
      vendor.
      
      * Force enable of IDE channels (used to be left alone as BIOS
        configured)
      
      * Change initial phase behavior of PIO cycle such that the host pulls
        down the bus instead of tristating it.  Vendor recommends this
        setting.
      
      The above settings are better for the current generation of
      controllers and needed for the upcoming next generation.
      
      Tested on JMB363.
      Signed-off-by: NTejun Heo <htejun@gmail.com>
      Cc: Ethan Hsiao <ethanhsiao@jmicron.com>
      Signed-off-by: NJeff Garzik <jeff@garzik.org>
      3a9e3a51
  11. 13 10月, 2007 3 次提交
  12. 29 9月, 2007 1 次提交
  13. 11 9月, 2007 1 次提交
  14. 23 8月, 2007 5 次提交
  15. 12 7月, 2007 3 次提交
  16. 01 6月, 2007 2 次提交