1. 15 6月, 2017 2 次提交
  2. 07 6月, 2017 1 次提交
  3. 21 3月, 2017 3 次提交
  4. 10 3月, 2017 3 次提交
    • M
      arm64: sysreg: add Set/Way sys encodings · 4dc52925
      Mark Rutland 提交于
      Cache maintenance ops fall in the SYS instruction class, and KVM needs
      to handle them. So as to keep all SYS encodings in one place, this
      patch adds them to sysreg.h.
      
      The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-2.
      
      To make it clear that these are instructions rather than registers, and
      to allow us to change the way these are handled in future, a new
      sys_insn() alias for sys_reg() is added and used for these new
      definitions.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      4dc52925
    • M
      arm64: sysreg: add register encodings used by KVM · 14ae7518
      Mark Rutland 提交于
      This patch adds sysreg definitions for registers which KVM needs the
      encodings for, which are not currently describe in <asm/sysregs.h>.
      Subsequent patches will make use of these definitions.
      
      The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-6, but
      this is not an exhaustive addition. Additions are only made for
      registers used today by KVM.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      14ae7518
    • M
      arm64: sysreg: add physical timer registers · 147a70ce
      Mark Rutland 提交于
      This patch adds sysreg definitions for system registers used to control
      the architected physical timer. Subsequent patches will make use of
      these definitions.
      
      The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-6.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      147a70ce
  5. 09 3月, 2017 4 次提交
    • M
      arm64: sysreg: subsume GICv3 sysreg definitions · 0e9884fe
      Mark Rutland 提交于
      Unlike most sysreg defintiions, the GICv3 definitions don't have a SYS_
      prefix, and they don't live in <asm/sysreg.h>. Additionally, some
      definitions are duplicated elsewhere (e.g. in the KVM save/restore
      code).
      
      For consistency, and to make it possible to share a common definition
      for these sysregs, this patch moves the definitions to <asm/sysreg.h>,
      adding a SYS_ prefix, and sorting the registers per their encoding.
      Existing users of the definitions are fixed up so that this change is
      not problematic.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      0e9884fe
    • M
      arm64: sysreg: add performance monitor registers · c7a3c61f
      Mark Rutland 提交于
      This patch adds sysreg definitions for system registers which are part
      of the performance monitors extension. Subsequent patches will make use
      of these definitions.
      
      The set of registers is described in ARM DDI 0487A.k_iss10775, Table
      D5-9. The encodings were taken from Table C5-6 in the same document.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      c7a3c61f
    • M
      arm64: sysreg: add debug system registers · d9801207
      Mark Rutland 提交于
      This patch adds sysreg definitions for system registers in the debug and
      trace system register encoding space. Subsequent patches will make use
      of these definitions.
      
      The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-5.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      d9801207
    • M
      arm64: sysreg: sort by encoding · 47863d41
      Mark Rutland 提交于
      Out sysreg definitions are largely (but not entirely) in ascending order
      of op0:op1:CRn:CRm:op2.
      
      It would be preferable to enforce this sort, as this makes it easier to
      verify the set of encodings against documentation, and provides an
      obvious location for each addition in future, minimising conflicts.
      
      This patch enforces this order, by moving the few items that break it.
      There should be no functional change.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      47863d41
  6. 12 1月, 2017 1 次提交
  7. 11 1月, 2017 1 次提交
  8. 10 1月, 2017 1 次提交
  9. 06 12月, 2016 1 次提交
  10. 02 12月, 2016 1 次提交
  11. 18 10月, 2016 1 次提交
    • W
      arm64: sysreg: Fix use of XZR in write_sysreg_s · 91cb163e
      Will Deacon 提交于
      Commit 8a71f0c6 ("arm64: sysreg: replace open-coded mrs_s/msr_s with
      {read,write}_sysreg_s") introduced a write_sysreg_s macro for writing
      to system registers that are not supported by binutils.
      
      Unfortunately, this was implemented with the wrong template (%0 vs %x0),
      so in the case that we are writing a constant 0, we will generate
      invalid instruction syntax and bail with a cryptic assembler error:
      
        | Error: constant expression required
      
      This patch fixes the template.
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      91cb163e
  12. 10 9月, 2016 1 次提交
  13. 09 9月, 2016 3 次提交
    • S
      arm64: Work around systems with mismatched cache line sizes · 116c81f4
      Suzuki K Poulose 提交于
      Systems with differing CPU i-cache/d-cache line sizes can cause
      problems with the cache management by software when the execution
      is migrated from one to another. Usually, the application reads
      the cache size on a CPU and then uses that length to perform cache
      operations. However, if it gets migrated to another CPU with a smaller
      cache line size, things could go completely wrong. To prevent such
      cases, always use the smallest cache line size among the CPUs. The
      kernel CPU feature infrastructure already keeps track of the safe
      value for all CPUID registers including CTR. This patch works around
      the problem by :
      
      For kernel, dynamically patch the kernel to read the cache size
      from the system wide copy of CTR_EL0.
      
      For applications, trap read accesses to CTR_EL0 (by clearing the SCTLR.UCT)
      and emulate the mrs instruction to return the system wide safe value
      of CTR_EL0.
      
      For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0
      via read_system_reg), we keep track of the pointer to table entry for
      CTR_EL0 in the CPU feature infrastructure.
      
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      116c81f4
    • M
      arm64: simplify sysreg manipulation · adf75899
      Mark Rutland 提交于
      A while back we added {read,write}_sysreg accessors to handle accesses
      to system registers, without the usual boilerplate asm volatile,
      temporary variable, etc.
      
      This patch makes use of these across arm64 to make code shorter and
      clearer. For sequences with a trailing ISB, the existing isb() macro is
      also used so that asm blocks can be removed entirely.
      
      A few uses of inline assembly for msr/mrs are left as-is. Those
      manipulating sp_el0 for the current thread_info value have special
      clobber requiremends.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      adf75899
    • M
      arm64: sysreg: allow write_sysreg to use XZR · 7aff4a2d
      Mark Rutland 提交于
      Currently write_sysreg has to allocate a temporary register to write
      zero to a system register, which is unfortunate given that the MSR
      instruction accepts XZR as an operand.
      
      Allow XZR to be used when appropriate by fiddling with the assembly
      constraints.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Reviewed-by: NRobin Murphy <robin.murphy@arm.com>
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      7aff4a2d
  14. 01 7月, 2016 1 次提交
    • A
      arm64: trap userspace "dc cvau" cache operation on errata-affected core · 7dd01aef
      Andre Przywara 提交于
      The ARM errata 819472, 826319, 827319 and 824069 for affected
      Cortex-A53 cores demand to promote "dc cvau" instructions to
      "dc civac". Since we allow userspace to also emit those instructions,
      we should make sure that "dc cvau" gets promoted there too.
      So lets grasp the nettle here and actually trap every userland cache
      maintenance instruction once we detect at least one affected core in
      the system.
      We then emulate the instruction by executing it on behalf of userland,
      promoting "dc cvau" to "dc civac" on the way and injecting access
      fault back into userspace.
      Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      [catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      7dd01aef
  15. 28 4月, 2016 1 次提交
  16. 20 4月, 2016 1 次提交
  17. 13 4月, 2016 1 次提交
  18. 31 3月, 2016 1 次提交
  19. 19 2月, 2016 1 次提交
    • J
      arm64: kernel: Add support for User Access Override · 57f4959b
      James Morse 提交于
      'User Access Override' is a new ARMv8.2 feature which allows the
      unprivileged load and store instructions to be overridden to behave in
      the normal way.
      
      This patch converts {get,put}_user() and friends to use ldtr*/sttr*
      instructions - so that they can only access EL0 memory, then enables
      UAO when fs==KERNEL_DS so that these functions can access kernel memory.
      
      This allows user space's read/write permissions to be checked against the
      page tables, instead of testing addr<USER_DS, then using the kernel's
      read/write permissions.
      Signed-off-by: NJames Morse <james.morse@arm.com>
      [catalin.marinas@arm.com: move uao_thread_switch() above dsb()]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      57f4959b
  20. 18 2月, 2016 1 次提交
  21. 17 2月, 2016 1 次提交
  22. 14 12月, 2015 1 次提交
  23. 21 10月, 2015 2 次提交
    • S
      arm64: Keep track of CPU feature registers · 3c739b57
      Suzuki K. Poulose 提交于
      This patch adds an infrastructure to keep track of the CPU feature
      registers on the system. For each register, the infrastructure keeps
      track of the system wide safe value of the feature bits. Also, tracks
      the which fields of a register should be matched strictly across all
      the CPUs on the system for the SANITY check infrastructure.
      
      The feature bits are classified into following 3 types depending on
      the implication of the possible values. This information is used to
      decide the safe value for a feature.
      
      LOWER_SAFE  - The smaller value is safer
      HIGHER_SAFE - The bigger value is safer
      EXACT       - We can't decide between the two, so a predefined safe_value is used.
      
      This infrastructure will be later used to make better decisions for:
      
       - Kernel features (e.g, KVM, Debug)
       - SANITY Check
       - CPU capability
       - ELF HWCAP
       - Exposing CPU Feature register to userspace.
      Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: NDave Martin <Dave.Martin@arm.com>
      [catalin.marinas@arm.com: whitespace fix]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      3c739b57
    • S
      arm64: Move mixed endian support detection · cdcf817b
      Suzuki K. Poulose 提交于
      Move the mixed endian support detection code to cpufeature.c
      from cpuinfo.c. This also moves the update_cpu_features()
      used by mixed endian detection code, which will get more
      functionality.
      
      Also moves the ID register field shifts to asm/sysreg.h,
      where all the useful definitions will end up in later patches.
      Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: NDave Martin <Dave.Martin@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      cdcf817b
  24. 20 10月, 2015 2 次提交
  25. 27 7月, 2015 3 次提交
  26. 25 7月, 2014 1 次提交