1. 21 8月, 2015 4 次提交
  2. 20 8月, 2015 3 次提交
  3. 12 8月, 2015 6 次提交
  4. 23 7月, 2015 2 次提交
  5. 22 7月, 2015 1 次提交
  6. 21 7月, 2015 1 次提交
    • R
      PCI: xilinx: Check for MSI interrupt flag before handling as INTx · e4a8f8ee
      Russell Joyce 提交于
      Occasionally both MSI and INTx bits in the interrupt decode register are
      set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the interrupt
      message should be checked to ensure that the correct handler is used.
      
      If this check is not in place and the interrupt message type is MSI, the
      INTx handler will be used erroneously when both type bits are set.  This
      will also be followed by a second read of the message FIFO, which can
      result in the function returning early and the interrupt decode register
      not being cleared if the FIFO is now empty.
      Signed-off-by: NRussell Joyce <russell.joyce@york.ac.uk>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      e4a8f8ee
  7. 15 7月, 2015 2 次提交
  8. 26 6月, 2015 2 次提交
  9. 25 6月, 2015 1 次提交
    • T
      PCI/keystone: Fix race in installing chained IRQ handler · 2cf5a03c
      Thomas Gleixner 提交于
      Fix a race where a pending interrupt could be received and the handler
      called before the handler's data has been setup, by converting to
      irq_set_chained_handler_and_data().
      
      Search and conversion was done with coccinelle:
      
      @@
      expression E1, E2, E3;
      @@
      (
      -if (irq_set_chained_handler(E1, E3) != 0)
      -   BUG();
      |
      -irq_set_chained_handler(E1, E3);
      )
      -irq_set_handler_data(E1, E2);
      +irq_set_chained_handler_and_data(E1, E3, E2);
      
      @@
      expression E1, E2, E3;
      @@
      (
      -if (irq_set_chained_handler(E1, E3) != 0)
      -   BUG();
      ...
      |
      -irq_set_chained_handler(E1, E3);
      ...
      )
      -irq_set_handler_data(E1, E2);
      +irq_set_chained_handler_and_data(E1, E3, E2);
      Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Julia Lawall <Julia.Lawall@lip6.fr>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: linux-pci@vger.kernel.org
      Cc: linux-arm-kernel@lists.infradead.org
      2cf5a03c
  10. 19 6月, 2015 2 次提交
  11. 16 6月, 2015 2 次提交
  12. 13 6月, 2015 1 次提交
  13. 11 6月, 2015 4 次提交
  14. 06 6月, 2015 1 次提交
    • D
      PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver · dcd19de3
      Duc Dang 提交于
      APM X-Gene v1 SoC supports its own implementation of MSI, which is not
      compliant to GIC V2M specification for MSI Termination.
      
      There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
      This MSI block supports 2048 MSI termination ports coalesced into 16
      physical HW IRQ lines and shared across all 5 PCIe ports.
      
      As there are only 16 HW IRQs to serve 2048 MSI vectors, to support
      set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically
      allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores).  To steer MSI
      interrupt to target CPU, MSI vector is moved around these HW IRQs lines.
      With this approach, the total MSI vectors this driver supports is reduced
      to 256.
      
      [bhelgaas: squash doc, driver, maintainer update]
      Signed-off-by: NDuc Dang <dhdang@apm.com>
      Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
      dcd19de3
  15. 03 6月, 2015 1 次提交
  16. 28 5月, 2015 4 次提交
  17. 27 5月, 2015 1 次提交
  18. 21 5月, 2015 2 次提交