- 21 8月, 2015 4 次提交
-
-
由 Bjorn Helgaas 提交于
of_parse_phandle() returns a device_node pointer with the refcount incremented. We should dispose of this reference when we're finished. Drop the reference acquired by of_parse_phandle(). Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-
由 Lorenzo Pieralisi 提交于
ARM previously stored the msi_controller pointer in its sysdata, struct pci_sys_data, and implemented pcibios_msi_controller() to retrieve it. That made PCI host controller drivers specific to ARM because they had to put the msi_controller pointer in the ARM-specific pci_sys_data. There is now a generic mechanism, pci_scan_root_bus_msi(), for giving the msi_controller pointer to the PCI core. Use this for all ARM systems and for the DesignWare and Xilinx PCI host controller drivers. This removes an ARM dependency from the DesignWare, DRA7xx, EXYNOS, i.MX6, Keystone, Layerscape, SPEAr13xx, and Xilinx drivers. [bhelgaas: changelog, split into separate patch] Suggested-by: NRussell King <linux@arm.linux.org.uk> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jingoohan1@gmail.com> CC: Pratyush Anand <pratyush.anand@gmail.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Simon Horman <horms@verge.net.au> CC: Russell King <linux@arm.linux.org.uk> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Thierry Reding <thierry.reding@gmail.com> CC: Michal Simek <michal.simek@xilinx.com> CC: Marc Zyngier <marc.zyngier@arm.com>
-
由 Jayachandran C 提交于
Make pci-host-generic driver (kernel option PCI_HOST_GENERIC) available on arm64. Signed-off-by: NJayachandran C <jchandra@broadcom.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Jayachandran C 提交于
The generic OF-based host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Note that the ARM pcibios functions expect the PCI sysdata to be a pointer to a struct pci_sys_data. Add a struct pci_sys_data as the first element in struct gen_pci so that when we use a gen_pci pointer as sysdata, it is also a pointer to a struct pci_sys_data. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: changelog, move pcie_bus_configure_settings() before pci_bus_add_devices(), combine !PCI_PROBE_ONLY blocks] Tested-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: NPavel Fedin <p.fedin@samsung.com> Signed-off-by: NJayachandran C <jchandra@broadcom.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-
- 20 8月, 2015 3 次提交
-
-
由 Fabio Estevam 提交于
Simplify a trivial if-return sequence by combining it with a preceding function call. The semantic patch that makes this change is available in scripts/coccinelle/misc/simple_return.cocci. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Lucas Stach <l.stach@pengutronix.de>
-
由 Fabio Estevam 提交于
Use BUG_ON() instead of an if condition followed by BUG(). The semantic patch that makes this change is available in scripts/coccinelle/misc/bugon.cocci. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
-
由 Fabio Estevam 提交于
There is no need to use the IS_ERR_VALUE() macro for checking the return value from pm_runtime_* functions. Test for a negative pm_runtime_get_sync() return value instead of using IS_ERR_VALUE(). The semantic patch that makes this change is available in scripts/coccinelle/api/pm_runtime.cocci. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Kishon Vijay Abraham I <kishon@ti.com>
-
- 12 8月, 2015 6 次提交
-
-
由 Kishon Vijay Abraham I 提交于
The PERST# line in am57x-evm is connected to a GPIO line and PERST# should be driven high to indicate the clocks are stable (As per Figure 2-10: Power Up of the PCIe CEM spec 3.0). Add support to make GPIO drive PERST# line. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Kishon Vijay Abraham I 提交于
DRA7xx requires the MSE bit to be cleared to set the master in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe Controller Master Standby Behavior advises to use the clearing of the local MSE bit to set the master in standby. Without this some of the clocks do not idle). Clear the MSE bit on suspend and enable it on resume. Clearing MSE bit is required to get clocks to be idled after suspend. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NJingoo Han <jingoohan1@gmail.com>
-
由 Kishon Vijay Abraham I 提交于
Add PM support to pci-dra7xx so PCI clocks can be disabled during suspend and enabled during resume without affecting PCI functionality. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NJingoo Han <jingoohan1@gmail.com>
-
由 Kishon Vijay Abraham I 提交于
Fix the error handling when pm_runtime_get_sync() fails. If pm_runtime_get_sync() fails, call pm_runtime_disable() so there are no unbalanced pm_runtime_enable() calls. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NJingoo Han <jingoohan1@gmail.com>
-
由 Hauke Mehrtens 提交于
Change CONFIG_PCIE_IPROC_BCMA to tristate to make it possible to build this driver as a module. Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRay Jui <rjui@broadcom.com>
-
由 Rob Herring 提交于
set_irq_flags is ARM-specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions, and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE, and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: NRob Herring <robh@kernel.org> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jingoohan1@gmail.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Thierry Reding <thierry.reding@gmail.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Alexandre Courbot <gnurou@gmail.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Pratyush Anand <pratyush.anand@gmail.com> CC: Simon Horman <horms@verge.net.au> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
-
- 23 7月, 2015 2 次提交
-
-
由 Murali Karicheri 提交于
Currently on Keystone SoCs, we always complain: keystone-pcie 21021000.pcie: missing *config* reg space Keystone uses an older version of DesignWare hardware that doesn't have ATU support. So va_cfg0_base and va_cfg1_base are already set up in ks_dw_pcie_host_init() before calling dw_pcie_host_init(), and they point to the remote config space address va (both same for Keystone). Add a check to avoid this boot noise on Keystone. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Ray Jui 提交于
Add arm64 support to the iProc PCIe driver. Note that on arm32, bus->sysdata points to the arm32-specific pci_sys_data struct, and pci_sys_data.private_data contains the iproc_pcie pointer. For arm64, there's nothing corresponding to pci_sys_data, so we keep the iproc_pcie pointer directly in bus->sysdata. In addition, arm64 does IRQ mapping in pcibios_add_device(), so it doesn't need pci_fixup_irqs() as arm32 does. Signed-off-by: NRay Jui <rjui@broadcom.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NScott Branden <sbranden@broadcom.com>
-
- 22 7月, 2015 1 次提交
-
-
由 Duc Dang 提交于
X-Gene PCIe controller has registers to support multiple memory ranges. Add support for a 64-bit prefetchable memory window. [bhelgaas: changelog] Signed-off-by: NDuc Dang <dhdang@apm.com> Signed-off-by: NTanmay Inamdar <tinamdar@apm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 21 7月, 2015 1 次提交
-
-
由 Russell Joyce 提交于
Occasionally both MSI and INTx bits in the interrupt decode register are set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the interrupt message should be checked to ensure that the correct handler is used. If this check is not in place and the interrupt message type is MSI, the INTx handler will be used erroneously when both type bits are set. This will also be followed by a second read of the message FIFO, which can result in the function returning early and the interrupt decode register not being cleared if the FIFO is now empty. Signed-off-by: NRussell Joyce <russell.joyce@york.ac.uk> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 15 7月, 2015 2 次提交
-
-
由 Krzysztof Kozlowski 提交于
platform_driver_register() automatically supplies THIS_MODULE, so we don't need to set it in the platform_driver struct. Remove the xgene_msi_driver.owner assignment. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Markus Elfring 提交于
The functions phy_exit() and phy_power_off() test whether their argument is NULL and then return immediately. Thus the test around the calls is not needed. This issue was detected by using the Coccinelle software. [bhelgaas: also phy_init() and phy_power_on(), as Ray Jui suggested] [bhelgaas: also remove tests in iproc_pcie_remove()] Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NRay Jui <rjui@broadcom.com>
-
- 26 6月, 2015 2 次提交
-
-
由 Pratyush Anand 提交于
Mohit's email-id doesn't exist anymore as he has left the company. Replace ST's id with mohit.kumar.dhaka@gmail.com. Signed-off-by: NPratyush Anand <pratyush.anand@gmail.com> Cc: Mohit Kumar <mohit.kumar.dhaka@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
-
由 Pratyush Anand 提交于
pratyush.anand@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with pratyush.anand@gmail.com. Signed-off-by: NPratyush Anand <pratyush.anand@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
-
- 25 6月, 2015 1 次提交
-
-
由 Thomas Gleixner 提交于
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org
-
- 19 6月, 2015 2 次提交
-
-
由 Duc Dang 提交于
Previously, when a Root Port's link was down, we didn't allow config access to the Root Port, which meant that if the Root Port led to an empty slot, "lspci" didn't even show the Root Port. Allow config access to Root Port even when link is down. [bhelgaas: changelog, fold in unused var fix] Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NDuc Dang <dhdang@apm.com> Signed-off-by: NTanmay Inamdar <tinamdar@apm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Duc Dang 提交于
When a CPU reads the Vendor and Device ID of a non-existent device, the controller should fabricate return data of 0xFFFFFFFF. Configuration Request Retry Status (CRS) is not applicable in this case because the device doesn't exist at all. The X-Gene v1 PCIe controller has a bug in the CRS logic such that when CRS is enabled, it fabricates return data of 0xFFFF0001 for this case, which means "the device exists but is not ready." That causes the PCI core to retry the read until it times out after 60 seconds. Disable CRS capability advertisement by clearing the CRS Software Visibility bit in the Root Capabilities Register. [bhelgaas: changelog and comment] Tested-by: NIan Campbell <ian.campbell@citrix.com> Tested-by: NMarcin Juszkiewicz <mjuszkiewicz@redhat.com> Signed-off-by: NDuc Dang <dhdang@apm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NTanmay Inamdar <tinamdar@apm.com>
-
- 16 6月, 2015 2 次提交
-
-
由 Bjorn Helgaas 提交于
Define PCIE_RC_LCSR and use it instead of the bare offset "0x80." No functional change. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Bjorn Helgaas 提交于
Use "u32", not "uint32_t", for consistency. Use "tmp", not "temp", for consistency within the driver. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRichard Zhu <Richard.Zhu@freescale.com>
-
- 13 6月, 2015 1 次提交
-
-
由 Troy Kisky 提交于
Currently, the timeout is never detected as count has a value of -1 if a timeout happens, but the code is checking for 0. Also, this patch removes the unneeded final wait if a timeout occurs. [bhelgaas: reworked starting from http://lkml.kernel.org/r/1433543864-7252-1-git-send-email-troy.kisky@boundarydevices.com] Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 11 6月, 2015 4 次提交
-
-
由 Bjorn Helgaas 提交于
All the DesignWare-based host drivers loop waiting for the link to come up, but they do it several ways that are needlessly different. Wait for the link to come up in a consistent style across all the DesignWare drivers. No functional change. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-
由 Bjorn Helgaas 提交于
All other DesignWare-based drivers have a *_establish_link() function. This functionality is trivial for Layerscape, but factor out a ls_pcie_establish_link() for consistency with the other drivers. No functional change. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-
由 Bjorn Helgaas 提交于
All the other DesignWare-based drivers use dw_pcie_link_up(), so use it in this driver, too, for consistency. No functional change. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-
由 Bjorn Helgaas 提交于
We already use dw_pcie_link_up() once in dra7xx_pcie_establish_link(), but we duplicate its code later. Use dw_pcie_link_up() for consistency. No functional change. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-
- 06 6月, 2015 1 次提交
-
-
由 Duc Dang 提交于
APM X-Gene v1 SoC supports its own implementation of MSI, which is not compliant to GIC V2M specification for MSI Termination. There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. This MSI block supports 2048 MSI termination ports coalesced into 16 physical HW IRQ lines and shared across all 5 PCIe ports. As there are only 16 HW IRQs to serve 2048 MSI vectors, to support set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores). To steer MSI interrupt to target CPU, MSI vector is moved around these HW IRQs lines. With this approach, the total MSI vectors this driver supports is reduced to 256. [bhelgaas: squash doc, driver, maintainer update] Signed-off-by: NDuc Dang <dhdang@apm.com> Signed-off-by: NTanmay Inamdar <tinamdar@apm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
-
- 03 6月, 2015 1 次提交
-
-
由 Bjorn Helgaas 提交于
Rename imx6_pcie_start_link() to imx6_pcie_establish_link() to follow the convention of other DesignWare-based host drivers. No functional change. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-
- 28 5月, 2015 4 次提交
-
-
由 Hauke Mehrtens 提交于
The resource list is only used in the setup process and was never freed. pci_add_resource() allocates a memory area to store the list item. Fix the memory leak. Tested-by: NRay Jui <rjui@broadcom.com> Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NRay Jui <rjui@broadcom.com>
-
由 Hauke Mehrtens 提交于
The struct iproc_pcie.resources member was pointing to a stack variable and is invalid after the registration function returned. Remove this pointer and add a parameter to the function. Tested-by: NRay Jui <rjui@broadcom.com> Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NRay Jui <rjui@broadcom.com>
-
由 Yijing Wang 提交于
After b97ea289 ("PCI: Assign resources before drivers claim devices (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so it is equivalent to: pci_create_root_bus() pci_scan_child_bus() Use pci_scan_root_bus() to simplify the code. [bhelgaas: changelog] Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NJingoo Han <jingoohan1@gmail.com> CC: Mohit Kumar <mohit.kumar@st.com>
-
由 Yijing Wang 提交于
After b97ea289 ("PCI: Assign resources before drivers claim devices (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so it is equivalent to tegra_pcie_scan_bus(). Remove tegra_pcie_scan_bus() (the hw.scan method), so we use the generic pci_scan_root_bus() path. [bhelgaas: changelog] Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NThierry Reding <treding@nvidia.com>
-
- 27 5月, 2015 1 次提交
-
-
由 Yijing Wang 提交于
After b97ea289 ("PCI: Assign resources before drivers claim devices (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so it is equivalent to mvebu_pcie_scan_bus(). Remove mvebu_pcie_scan_bus() (the hw.scan method), so we use the generic pci_scan_root_bus() path. We also need to use pci_common_init_dev() instead of pci_common_init() so we can supply the host bridge device pointer. [bhelgaas: changelog] Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Jason Cooper <jason@lakedaemon.net>
-
- 21 5月, 2015 2 次提交
-
-
由 Jisheng Zhang 提交于
Most transactions' type are cfg0 and MEM, so the current iATU usage is not balanced: iATU0 is hot while iATU1 is rarely used. Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM. This allocation idea comes from Minghuan Lian <Minghuan.Lian@freescale.com>: [bhelgaas: use link with Message-ID] Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.comSigned-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-
由 Jisheng Zhang 提交于
Currently, the outbound iATU programming functions are similar: the only difference is index, type, addr and size. Consolidate these functions into one. This saves about 1700 bytes in text: text data bss dec hex filename 9276 204 4 9484 250c pcie-designware.o-before 7532 204 4 7740 1e3c pcie-designware.o Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
-