1. 07 1月, 2014 1 次提交
  2. 15 7月, 2013 1 次提交
    • P
      x86: delete __cpuinit usage from all x86 files · 148f9bb8
      Paul Gortmaker 提交于
      The __cpuinit type of throwaway sections might have made sense
      some time ago when RAM was more constrained, but now the savings
      do not offset the cost and complications.  For example, the fix in
      commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
      is a good example of the nasty type of bugs that can be created
      with improper use of the various __init prefixes.
      
      After a discussion on LKML[1] it was decided that cpuinit should go
      the way of devinit and be phased out.  Once all the users are gone,
      we can then finally remove the macros themselves from linux/init.h.
      
      Note that some harmless section mismatch warnings may result, since
      notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
      are flagged as __cpuinit  -- so if we remove the __cpuinit from
      arch specific callers, we will also get section mismatch warnings.
      As an intermediate step, we intend to turn the linux/init.h cpuinit
      content into no-ops as early as possible, since that will get rid
      of these warnings.  In any case, they are temporary and harmless.
      
      This removes all the arch/x86 uses of the __cpuinit macros from
      all C files.  x86 only had the one __CPUINIT used in assembly files,
      and it wasn't paired off with a .previous or a __FINIT, so we can
      delete it directly w/o any corresponding additional change there.
      
      [1] https://lkml.org/lkml/2013/5/20/589
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: x86@kernel.org
      Acked-by: NIngo Molnar <mingo@kernel.org>
      Acked-by: NThomas Gleixner <tglx@linutronix.de>
      Acked-by: NH. Peter Anvin <hpa@linux.intel.com>
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      148f9bb8
  3. 22 2月, 2012 1 次提交
    • S
      x86/tsc: Reduce the TSC sync check time for core-siblings · b0e5c779
      Suresh Siddha 提交于
      For each logical CPU that is coming online, we spend 20msec for
      checking the TSC synchronization. And as this is done
      sequentially for each logical CPU boot, this time gets added up
      depending on the number of logical CPU's supported by the
      platform.
      
      Minimize this by using the socket topology information.
      
      If the target CPU coming online doesn't have any of its
      core-siblings online, a timeout of 20msec will be used for the
      TSC-warp measurement loop. Otherwise a smaller timeout of 2msec
      will be used, as we have some information about this socket
      already (and this information grows as we have more and more
      logical-siblings in that socket).
      
      Ideally we should be able to skip the TSC sync check on the
      other core-siblings, if the first logical CPU in a socket passed
      the sync test. But as the TSC is per-logical CPU and can
      potentially be modified wrongly by the bios before the OS boot,
      TSC sync test for smaller duration should be able to catch such
      errors. Also this will catch the condition where all the cores
      in the socket doesn't get reset at the same time.
      
      For example, with this modification, time spent in TSC sync
      checks on a 4 socket 10-core with HT system gets reduced from
      1580msec to 212msec.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Acked-by: NArjan van de Ven <arjan@linux.intel.com>
      Acked-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Jack Steiner <steiner@sgi.com>
      Cc: venki@google.com
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Link: http://lkml.kernel.org/r/1328581940.29790.20.camel@sbsiddha-desk.sc.intel.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
      b0e5c779
  4. 06 12月, 2011 1 次提交
  5. 15 12月, 2009 3 次提交
  6. 26 11月, 2009 1 次提交
    • M
      x86: Limit number of per cpu TSC sync messages · 9b3660a5
      Mike Travis 提交于
      Limit the number of per cpu TSC sync messages by only printing
      to the console if an error occurs, otherwise print as a DEBUG
      message.
      
      The info message "Skipping synchronization ..." is only printed
      after the last cpu has booted.
      Signed-off-by: NMike Travis <travis@sgi.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Roland Dreier <rdreier@cisco.com>
      Cc: Randy Dunlap <rdunlap@xenotime.net>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Andi Kleen <andi@firstfloor.org>
      Cc: Greg Kroah-Hartman <gregkh@suse.de>
      Cc: Yinghai Lu <yhlu.kernel@gmail.com>
      Cc: David Rientjes <rientjes@google.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Cc: Jack Steiner <steiner@sgi.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <20091118002222.181053000@alcatraz.americas.sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      9b3660a5
  7. 24 9月, 2009 1 次提交
    • R
      x86: Reduce verbosity of "TSC is reliable" message · ea01c0d7
      Roland Dreier 提交于
      On modern systems, the kernel prints the message
      
          Skipping synchronization checks as TSC is reliable.
      
      once for every non-boot CPU.
      
      This gets kind of ridiculous on huge systems; for example, on a
      64-thread system I was lucky enough to get:
      
          $ dmesg | grep 'TSC is reliable' | wc
               63     567    4221
      
      There's no point to doing this for every CPU, since the code is
      just checking the boot CPU anyway, so change this to a
      printk_once() to make the message appears only once.
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      LKML-Reference: <adazl8l2swc.fsf@cisco.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ea01c0d7
  8. 07 5月, 2009 1 次提交
  9. 18 11月, 2008 1 次提交
    • V
      x86: add rdtsc barrier to TSC sync check · 93ce99e8
      Venki Pallipadi 提交于
      Impact: fix incorrectly marked unstable TSC clock
      
      Patch (commit 0d12cdd5 "sched: improve sched_clock() performance") has
      a regression on one of the test systems here.
      
      With the patch, I see:
      
       checking TSC synchronization [CPU#0 -> CPU#1]:
       Measured 28 cycles TSC warp between CPUs, turning off TSC clock.
       Marking TSC unstable due to check_tsc_sync_source failed
      
      Whereas, without the patch syncs pass fine on all CPUs:
      
       checking TSC synchronization [CPU#0 -> CPU#1]: passed.
      
      Due to this, TSC is marked unstable, when it is not actually unstable.
      This is because syncs in check_tsc_wrap() goes away due to this commit.
      
      As per the discussion on this thread, correct way to fix this is to add
      explicit syncs as below?
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      93ce99e8
  10. 02 11月, 2008 1 次提交
    • A
      x86: Add a synthetic TSC_RELIABLE feature bit. · eca0cd02
      Alok Kataria 提交于
      Impact: Changes timebase calibration on Vmware.
      
      Use the synthetic TSC_RELIABLE bit to workaround virtualization anomalies.
      
      Virtual TSCs can be kept nearly in sync, but because the virtual TSC
      offset is set by software, it's not perfect.  So, the TSC
      synchronization test can fail. Even then the TSC can be used as a
      clocksource since the VMware platform exports a reliable TSC to the
      guest for timekeeping purposes. Use this bit to check if we need to
      skip the TSC sync checks.
      
      Along with this also set the CONSTANT_TSC bit when on VMware, since we
      still want to use TSC as clocksource on VM running over hardware which
      has unsynchronized TSC's (opteron's), since the hypervisor will take
      care of providing consistent TSC to the guest.
      Signed-off-by: NAlok N Kataria <akataria@vmware.com>
      Signed-off-by: NDan Hecht <dhecht@vmware.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      eca0cd02
  11. 21 8月, 2008 1 次提交
  12. 30 1月, 2008 4 次提交
    • I
      x86: add warning to check_tsc_warp() · ad8ca495
      Ingo Molnar 提交于
      add warning to check_tsc_warp() - if get_cycles() does not progress.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      ad8ca495
    • I
      x86: check_tsc_warp() slowness fix · df43510b
      Ingo Molnar 提交于
      100 million max # of loops is a bit too much - reduce it to 10 million.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      df43510b
    • A
      x86: remove get_cycles_sync · 6d63de8d
      Andi Kleen 提交于
      rdtsc is now speculation-safe, so no need for the sync variants of
      the APIs.
      
      [ mingo@elte.hu: removed the nsec_barrier() complication. ]
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      6d63de8d
    • M
      x86: fix: s2ram + P4 + tsc = annoyance · 4c6b8b4d
      Mike Galbraith 提交于
      s2ram recently became useful here, except for the kernel's annoying
      habit of disabling my P4's perfectly good TSC.
      
      [  107.894470] CPU 1 is now offline
      [  107.894474] SMP alternatives: switching to UP code
      [  107.895832] CPU0 attaching sched-domain:
      [  107.895836]  domain 0: span 1
      [  107.895838]   groups: 1
      [  107.896097] CPU1 is down
      [    3.726156] Intel machine check architecture supported.
      [    3.726165] Intel machine check reporting enabled on CPU#0.
      [    3.726167] CPU0: Intel P4/Xeon Extended MCE MSRs (12) available
      [    3.726170] CPU0: Thermal monitoring enabled
      [    3.726175] Back to C!
      [    3.726708] Force enabled HPET at resume
      [    3.726775] Enabling non-boot CPUs ...
      [    3.727049] CPU0 attaching NULL sched-domain.
      [    3.727165] SMP alternatives: switching to SMP code
      [    3.727858] Booting processor 1/1 eip 3000
      [    3.727862] CPU 1 irqstacks, hard=b042f000 soft=b042d000
      [    3.738173] Initializing CPU#1
      [    3.798912] Calibrating delay using timer specific routine.. 5986.12 BogoMIPS (lpj=2993061)
      [    3.798920] CPU: After generic identify, caps: bfebfbff 00000000 00000000 00000000 00004400 00000000 00000000 00000000
      [    3.798931] CPU: Trace cache: 12K uops, L1 D cache: 8K
      [    3.798934] CPU: L2 cache: 512K
      [    3.798936] CPU: Physical Processor ID: 0
      [    3.798938] CPU: After all inits, caps: bfebfbff 00000000 00000000 0000b080 00004400 00000000 00000000 00000000
      [    3.798946] Intel machine check architecture supported.
      [    3.798952] Intel machine check reporting enabled on CPU#1.
      [    3.798955] CPU1: Intel P4/Xeon Extended MCE MSRs (12) available
      [    3.798959] CPU1: Thermal monitoring enabled
      [    3.799161] CPU1: Intel(R) Pentium(R) 4 CPU 3.00GHz stepping 09
      [    3.799187] checking TSC synchronization [CPU#0 -> CPU#1]:
      [    3.819181] Measured 63588552840 cycles TSC warp between CPUs, turning off TSC clock.
      [    3.819184] Marking TSC unstable due to: check_tsc_sync_source failed.
      
      If check_tsc_warp() is called after initial boot, and the TSC has in the
      meantime been set (BIOS, user, silicon, elves) to a value lower than the
      last stored/stale value, we blame the TSC.  Reset to pristine condition
      after every test.
      Signed-off-by: NMike Galbraith <efault@gmx.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      4c6b8b4d
  13. 14 10月, 2007 1 次提交
    • D
      Delete filenames in comments. · 835c34a1
      Dave Jones 提交于
      Since the x86 merge, lots of files that referenced their own filenames
      are no longer correct.  Rather than keep them up to date, just delete
      them, as they add no real value.
      
      Additionally:
      - fix up comment formatting in scx200_32.c
      - Remove a credit from myself in setup_64.c from a time when we had no SCM
      - remove longwinded history from tsc_32.c which can be figured out from
        git.
      Signed-off-by: NDave Jones <davej@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      835c34a1
  14. 11 10月, 2007 2 次提交
  15. 17 2月, 2007 1 次提交