1. 21 7月, 2016 1 次提交
    • A
      x86/insn: Add AVX-512 support to the instruction decoder · 25af37f4
      Adrian Hunter 提交于
      Add support for Intel's AVX-512 instructions to the instruction decoder.
      
      AVX-512 instructions are documented in Intel Architecture Instruction
      Set Extensions Programming Reference (February 2016).
      
      AVX-512 instructions are identified by a EVEX prefix which, for the
      purpose of instruction decoding, can be treated as though it were a
      4-byte VEX prefix.
      
      Existing instructions which can now accept an EVEX prefix need not be
      further annotated in the op code map (x86-opcode-map.txt). In the case
      of new instructions, the op code map is updated accordingly.
      
      Also add associated Mask Instructions that are used to manipulate mask
      registers used in AVX-512 instructions.
      
      The 'perf tools' instruction decoder is updated in a subsequent patch.
      And a representative set of instructions is added to the perf tools new
      instructions test in a subsequent patch.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Acked-by: NIngo Molnar <mingo@kernel.org>
      Acked-by: NMasami Hiramatsu <mhiramat@kernel.org>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: X86 ML <x86@kernel.org>
      Link: http://lkml.kernel.org/r/1469003437-32706-3-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      25af37f4
  2. 20 7月, 2016 1 次提交
  3. 04 9月, 2015 5 次提交
    • A
      x86/insn: perf tools: Add new xsave instructions · f83b6b64
      Adrian Hunter 提交于
      Add xsavec, xsaves and xrstors to the op code map and the perf tools new
      instructions test.  To run the test:
      
        $ tools/perf/perf test "x86 ins"
        39: Test x86 instruction decoder - new instructions          : Ok
      
      Or to see the details:
      
        $ tools/perf/perf test -v "x86 ins" 2>&1 | grep 'xsave\|xrst'
      
      For information about xsavec, xsaves and xrstors, refer the Intel SDM.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Acked-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Qiaowei Ren <qiaowei.ren@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/1441196131-20632-8-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      f83b6b64
    • A
      x86/insn: perf tools: Add new memory protection keys instructions · 978260cd
      Adrian Hunter 提交于
      Add rdpkru and wrpkru to the op code map and the perf tools new
      instructions test.  In the case of the test, only the bytes can be
      tested at the moment since binutils doesn't support the instructions
      yet.  To run the test:
      
        $ tools/perf/perf test "x86 ins"
        39: Test x86 instruction decoder - new instructions          : Ok
      
      Or to see the details:
      
        $ tools/perf/perf test -v "x86 ins" 2>&1 | grep pkru
      
      For information about rdpkru and wrpkru, refer the Intel SDM.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Acked-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Qiaowei Ren <qiaowei.ren@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/1441196131-20632-7-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      978260cd
    • A
      x86/insn: perf tools: Add new memory instructions · ac1c8859
      Adrian Hunter 提交于
      Intel Architecture Instruction Set Extensions Programing Reference (Oct
      2014) describes 3 new memory instructions, namely clflushopt, clwb and
      pcommit.  Add them to the op code map and the perf tools new
      instructions test. e.g.
      
        $ tools/perf/perf test "x86 ins"
        39: Test x86 instruction decoder - new instructions          : Ok
      
      Or to see the details:
      
        $ tools/perf/perf test -v "x86 ins"
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Acked-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Qiaowei Ren <qiaowei.ren@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/1441196131-20632-6-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      ac1c8859
    • A
      x86/insn: perf tools: Add new SHA instructions · 3fe78d6a
      Adrian Hunter 提交于
      Intel SHA Extensions are explained in the Intel Architecture
      Instruction Set Extensions Programing Reference (Oct 2014).
      There are 7 new instructions.  Add them to the op code map
      and the perf tools new instructions test. e.g.
      
        $ tools/perf/perf test "x86 ins"
        39: Test x86 instruction decoder - new instructions          : Ok
      
      Or to see the details:
      
        $ tools/perf/perf test -v "x86 ins" 2>&1 | grep sha
      
      Committer note:
      
      3 lines of details, for the curious:
      
        $ perf test -v "x86 ins" 2>&1 | grep sha256msg1 | tail -3
        Decoded ok: 0f 38 cc 84 08 78 56 34 12 	sha256msg1 0x12345678(%rax,%rcx,1),%xmm0
        Decoded ok: 0f 38 cc 84 c8 78 56 34 12 	sha256msg1 0x12345678(%rax,%rcx,8),%xmm0
        Decoded ok: 44 0f 38 cc bc c8 78 56 34 12 	sha256msg1 0x12345678(%rax,%rcx,8),%xmm15
        $
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Acked-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Qiaowei Ren <qiaowei.ren@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/1441196131-20632-5-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      3fe78d6a
    • A
      x86/insn: perf tools: Pedantically tweak opcode map for MPX instructions · 78173ec6
      Adrian Hunter 提交于
      The MPX instructions are presently not described in the SDM
      opcode maps, and there are not encoding characters for bnd
      registers, address method or operand type.  So the kernel
      opcode map is using 'Gv' for bnd registers and 'Ev' for
      everything else.  That is fine because the instruction
      decoder does not use that information anyway, except as
      an indication that there is a ModR/M byte.
      
      Nevertheless, in some cases the 'Gv' and 'Ev' are the wrong
      way around, BNDLDX and BNDSTX have 2 operands not 3, and it
      wouldn't hurt to identify the mandatory prefixes.
      
      This has no effect on the decoding of valid instructions,
      but the addition of the mandatory prefixes will cause some
      invalid instructions to error out that wouldn't have
      previously.
      
      Note that perf tools has a copy of the instruction decoder
      and provides a test for new instructions which includes MPX
      instructions e.g.
      
        $ perf test "x86 ins"
        39: Test x86 instruction decoder - new instructions          : Ok
      
      Or to see the details:
      
        $ perf test -v "x86 ins"
      
      Commiter notes:
      
      And to see these MPX instructions specifically:
      
        $ perf test -v "x86 ins" 2>&1 | grep bndldx | head -3
        Decoded ok: 0f 1a 00             	bndldx (%eax),%bnd0
        Decoded ok: 0f 1a 05 78 56 34 12 	bndldx 0x12345678,%bnd0
        Decoded ok: 0f 1a 18             	bndldx (%eax),%bnd3
        $ perf test -v "x86 ins" 2>&1 | grep bndstx | head -3
        Decoded ok: 0f 1b 00             	bndstx %bnd0,(%eax)
        Decoded ok: 0f 1b 05 78 56 34 12 	bndstx %bnd0,0x12345678
        Decoded ok: 0f 1b 18             	bndstx %bnd3,(%eax)
        $
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Acked-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Qiaowei Ren <qiaowei.ren@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/1441196131-20632-4-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      78173ec6
  4. 19 2月, 2015 1 次提交
  5. 18 1月, 2014 1 次提交
  6. 06 8月, 2013 1 次提交
  7. 06 6月, 2012 1 次提交
    • M
      x86/decoder: Fix bsr/bsf/jmpe decoding with operand-size prefix · 436d03fa
      Masami Hiramatsu 提交于
      Fix the x86 instruction decoder to decode bsr/bsf/jmpe with
      operand-size prefix (66h). This fixes the test case failure
      reported by Linus, attached below.
      
      bsf/bsr/jmpe have a special encoding. Opcode map in
      Intel Software Developers Manual vol2 says they have
      TZCNT/LZCNT variants if it has F3h prefix. However, there
      is no information if it has other 66h or F2h prefixes.
      Current instruction decoder supposes that those are
      bad instructions, but it actually accepts at least
      operand-size prefixes.
      
      H. Peter Anvin further explains:
      
       " TZCNT/LZCNT are F3 + BSF/BSR exactly because the F2 and
         F3 prefixes have historically been no-ops with most instructions.
         This allows software to unconditionally use the prefixed versions
         and get TZCNT/LZCNT on the processors that have them if they don't
         care about the difference. "
      
      This fixes errors reported by test_get_len:
      
        Warning: arch/x86/tools/test_get_len found difference at <em_bsf>:ffffffff81036d87
        Warning: ffffffff81036de5:	66 0f bc c2          	bsf    %dx,%ax
        Warning: objdump says 4 bytes, but insn_get_length() says 3
        Warning: arch/x86/tools/test_get_len found difference at <em_bsr>:ffffffff81036ea6
        Warning: ffffffff81036f04:	66 0f bd c2          	bsr    %dx,%ax
        Warning: objdump says 4 bytes, but insn_get_length() says 3
        Warning: decoded and checked 13298882 instructions with 2 warnings
      Reported-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Reported-by: NPekka Enberg <penberg@kernel.org>
      Signed-off-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: <yrl.pp-manager.tt@hitachi.com>
      Link: http://lkml.kernel.org/r/20120604150911.22338.43296.stgit@localhost.localdomainSigned-off-by: NIngo Molnar <mingo@kernel.org>
      436d03fa
  8. 18 1月, 2012 1 次提交
  9. 16 1月, 2012 1 次提交
  10. 05 12月, 2011 1 次提交
  11. 29 10月, 2009 4 次提交
    • M
      x86: Add Intel FMA instructions to x86 opcode map · 3f7e454a
      Masami Hiramatsu 提交于
      Add Intel FMA(FUSED-MULTIPLY-ADD) instructions to x86 opcode map
      for x86 instruction decoder.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Frank Ch. Eigler <fche@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jason Baron <jbaron@redhat.com>
      Cc: K.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
      LKML-Reference: <20091027204235.30545.33997.stgit@harusame>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3f7e454a
    • M
      x86: AVX instruction set decoder support · e0e492e9
      Masami Hiramatsu 提交于
      Add Intel AVX(Advanced Vector Extensions) instruction set
      support to x86 instruction decoder. This adds insn.vex_prefix
      field for storing VEX prefixes, and introduces some original
      tags for expressing opcodes attributes.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Frank Ch. Eigler <fche@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jason Baron <jbaron@redhat.com>
      Cc: K.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
      LKML-Reference: <20091027204226.30545.23451.stgit@harusame>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e0e492e9
    • M
      x86: Add pclmulq to x86 opcode map · 82cb5702
      Masami Hiramatsu 提交于
      Add pclmulq opcode to x86 opcode map.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Frank Ch. Eigler <fche@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jason Baron <jbaron@redhat.com>
      Cc: K.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
      LKML-Reference: <20091027204219.30545.82039.stgit@harusame>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      82cb5702
    • M
      x86: Fix SSE opcode map bug · 7f387d3f
      Masami Hiramatsu 提交于
      Fix superscripts position because some superscripts of SSE
      opcode are not put in correct position.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Frank Ch. Eigler <fche@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jason Baron <jbaron@redhat.com>
      Cc: K.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
      LKML-Reference: <20091027204204.30545.97296.stgit@harusame>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7f387d3f
  12. 21 10月, 2009 1 次提交
  13. 17 10月, 2009 2 次提交
    • M
      x86: Add AMD prefetch and 3DNow! opcodes to opcode map · d1baf5a5
      Masami Hiramatsu 提交于
      Add AMD prefetch and 3DNow! opcode including FEMMS. Since 3DNow!
      uses the last immediate byte as an opcode extension byte, x86
      insn just treats the extenstion byte as an immediate byte
      instead of a part of opcode (insn_get_opcode() decodes first
      "0x0f 0x0f" bytes.)
      
      Users who are interested in analyzing 3DNow! opcode still can
      decode it by analyzing the immediate byte.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <20091017000744.16556.27881.stgit@dhcp-100-2-132.bos.redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d1baf5a5
    • M
      x86: Add MMX/SSE opcode groups to opcode map · 8c95bc3e
      Masami Hiramatsu 提交于
      Add missing MMX/SSE opcode groups to x86 opcode map.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <20091017000736.16556.29061.stgit@dhcp-100-2-132.bos.redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8c95bc3e
  14. 03 10月, 2009 1 次提交
    • M
      x86: Add VIA processor instructions in opcodes decoder · c0b11d3a
      Masami Hiramatsu 提交于
      Add VIA processor's Padlock instructions(MONTMUL, XSHA1, XSHA256)
      as parts of the kernel may use them.
      
      This fixes the following crash in opcodes decoder selftests:
      
       make[2]: `scripts/unifdef' is up to date.
         TEST    posttest
       Error: c145cf71:        f3 0f a6 d0             repz xsha256
       Error: objdump says 4 bytes, but insn_get_length() says 3 (attr:0)
       make[1]: *** [posttest] Error 2
       make: *** [bzImage] Error 2
      Reported-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Acked-by: NSteven Rostedt <rostedt@goodmis.org>
      Acked-by: NIngo Molnar <mingo@elte.hu>
      Cc: Jim Keniston <jkenisto@us.ibm.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Andi Kleen <ak@linux.intel.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Frank Ch. Eigler <fche@redhat.com>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Jason Baron <jbaron@redhat.com>
      Cc: K.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
      Cc: Li Zefan <lizf@cn.fujitsu.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
      Cc: Tom Zanussi <tzanussi@gmail.com>
      LKML-Reference: <20090925182037.10157.3180.stgit@omoto>
      Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
      c0b11d3a
  15. 11 9月, 2009 1 次提交
  16. 27 8月, 2009 1 次提交
    • M
      x86: Instruction decoder API · eb13296c
      Masami Hiramatsu 提交于
      Add x86 instruction decoder to arch-specific libraries. This decoder
      can decode x86 instructions used in kernel into prefix, opcode, modrm,
      sib, displacement and immediates. This can also show the length of
      instructions.
      
      This version introduces instruction attributes for decoding
      instructions.
      The instruction attribute tables are generated from the opcode map file
      (x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
      
      Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
      IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
      and consist of below two types of opcode tables.
      
      1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
      written as below;
      
       Table: table-name
       Referrer: escaped-name
       opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
        (or)
       opcode: escape # escaped-name
       EndTable
      
      Group opcodes, which has 8 elements, are written as below;
      
       GrpTable: GrpXXX
       reg:  mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
       EndTable
      
      These opcode maps include a few SSE and FP opcodes (for setup), because
      those opcodes are used in the kernel.
      Signed-off-by: NMasami Hiramatsu <mhiramat@redhat.com>
      Signed-off-by: NJim Keniston <jkenisto@us.ibm.com>
      Acked-by: NH. Peter Anvin <hpa@zytor.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: Avi Kivity <avi@redhat.com>
      Cc: Andi Kleen <ak@linux.intel.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Frank Ch. Eigler <fche@redhat.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Jason Baron <jbaron@redhat.com>
      Cc: K.Prasad <prasad@linux.vnet.ibm.com>
      Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
      Cc: Li Zefan <lizf@cn.fujitsu.com>
      Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
      Cc: Roland McGrath <roland@redhat.com>
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Tom Zanussi <tzanussi@gmail.com>
      Cc: Vegard Nossum <vegard.nossum@gmail.com>
      LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
      Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
      eb13296c