- 07 5月, 2010 32 次提交
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由 Sekhar Nori 提交于
In the edma driver, there are couple of instances where braces are used for a single statement 'if' construct. There are other instances where 'else' part of the if-else construct does not use braces even if the 'if' part is a multi-line statement. This patch fixes both. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
'edma_info' structure inside the edma driver represents a single instance of edma channel controller. Call it 'edma_cc' instead. This also avoids readers confusing it with an instance of edma_soc_info structre which carries the platform data for a single channel controller instance. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
With this patch, AR7 type uart ports are not reset via pwremu registers. This allows davinci_serial_init() reuse on tnetv107x soc. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
This patch implements davinci serial cleanups towards having this code reusable on tnetv107x. The change reuses the platform data membase field to hold the remapped space. By disabling the UPF_IOREMAP flag in the platform data, we prevent the 8250 driver from repeating the ioremap. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
The uart pdata array is already terminated by a zero flag field. This patch reuses this terminator and eliminates DAVINCI_MAX_NR_UARTS definition. This way, future platforms can have different number of uarts initialized via davinci_serial_init(). Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
The earlier watchdog reset mechanism had a couple of limitations. First, it embedded a reference to "davinci_wdt_device" inside common code. This forced all derived platforms (da8xx and tnetv107x) to define such a device. This also would have caused problems in including multiple socs in a single build due to symbol redefinition. With this patch, davinci_watchdog_reset() now takes the platform device as an argument. The davinci_soc_info struct has been extended to include a reset function and a watchdog platform_device. arch_reset() then uses these elements to reset the system in a SoC specific fashion. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Pinmux registers are sequential, and do not need to be enumerated out as they currently are. This reduces code volume and keeps things simple. If some future SoC comes up with a discontiguous register map, PINMUX() can then be expanded with local token pasting. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
This patch eliminates the global gpio_lock, and implements a per-controller lock instead. This also switches to irqsave/irqrestore locks in case gpios are manipulated in isr. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
This patch allows for gpio controllers that deviate from those found on traditional davinci socs. davinci_soc_info has an added field to indicate the soc-specific gpio controller type. The gpio initialization code then bails out if necessary. More elements (tnetv107x) to be added later into enum davinci_gpio_type. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
This patch renders the inlined gpio accessors in gpio.h independent of the underlying controller's register layout. This is done by including three new fields in davinci_gpio_controller to hold the addresses of the set, clear, and in data registers. Other changes: 1. davinci_gpio_regs structure definition moved to gpio.c. This structure is no longer common across all davinci socs (davinci_gpio_controller is). 2. controller base address calculation code (gpio2controller()) moved to gpio.c as this was no longer necessary for the inline implementation. 3. modified inline range checks to use davinci_soc_info.gpio_num instead of DAVINCI_N_GPIO. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Renamed gpio types to something more sensible: struct gpio_controller --> struct davinci_gpio_regs struct davinci_gpio --> struct davinci_gpio_controller gpio2controller() --> gpio2regs() irq2controller() --> irq2regs() This change also moves davinci_gpio_controller definition to gpio.h. Eventually, the gpio registers structure will be moved to gpio.c and no longer a common cross-soc definition. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
macroized repeated container_of()s to improve readability. unified direction in/out functions. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sergei Shtylyov 提交于
The IDE platform device is registered in three different places (2 board files for DM644x and in dm646x.c for DM646x) while both the IDE base address and the IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE platform seems to be in devices.c. Merge the IDE platform data and registration code and create davinci_init_ide() in place of dm646x_init_ide()... Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Thomas Koeller 提交于
linux/compiler.h is required for __iomem linux/types.h is required u32 Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
This patch allows socs to override the divider ratio mask by setting an optional field (div_ratio_mask) in the pll_data structure. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Tested-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Thomas Koeller 提交于
Extended the MUX configuration to allow use of GPIO terminals 64..57. Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sergei Shtylyov 提交于
The board file #define's its own version of EMIFA base addresses, while there are DA8XX_AEMIF_*_BASE macros #define'd in <mach/da8xx.h>. Start using them instead. Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sergei Shtylyov 提交于
Currently each DaVinci board file #define's its own version of the EMIFA base addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication. Move these #define's to the SoC specific headers, changing their prefixes from 'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses are SoC specific... And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet. Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Added tnetv107x cpu type definitions and cpu identification macros. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
IRQ numbers as defined for tnetv107x cp_intc. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Added definitions for LPSC modules in the tnetv107x SOC Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Added list of muxed pins on the tnetv107x SOC. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Rename da8xx_pinmux_setup() to davinci_cfg_reg_list() and promote it for use in other SOCs that may need the ability to configure multiple pins in one shot. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
The current clock control code always gates the clock (PSC state Disable = 2) on clk_disable(). Some on-chip peripherals (e.g. LCD controller on TNETV107X) need to be put into SwRstDisable = 0 on clock disable, to maintain hardware sanity. This patch extends the davinci_psc_config() arguments to pass in the desired module state instead of a boolean enable/disable. Further, clk_disable() now checks for the PSC_SWRSTDISABLE clk flag before selecting the target state. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Host map configuration instructs the interrupt controller to route interrupt channels to FIQ or IRQ lines. Currently, DA8xx family of devices leave these registers at their reset-default values. TNETV107X however does not have sane reset defaults, and therefore this architecture needs to reconfigure the host-map such that channels 0 and 1 go to FIQ, and the remaining channels raise IRQs. This patch adds an optional host map argument to cp_intc_init() for this. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
timer_init() programs timer64 hardware. The module should ideally be brought out of reset before this happens. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Cyril Chemparathy 提交于
Preliminary modification prior to adding support for TNETV107X based on ARM1176. This change allows for CPUs other than ARM926T to be used for Davinci derivative SoCs. Existing devices (DA8x and DMx) operate unchanged. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Anuj Aggarwal 提交于
Currently, the ISR in the EDMA driver clears the pending interrupt for all channels without regard to whether that channel has a registered callback or not. This causes problems for devices like DM355/DM365 where the multimedia accelerator uses EDMA by polling on the interrupt pending bits of some of the EDMA channels. Since these channels are actually allocated through the Linux EDMA driver (by an out-of-kernel module), the same shadow region is used by Linux and accelerator. There a race between the Linux ISR and the polling code running on the accelerator on the IPR (interrupt pending register). This patch fixes the issue by making the ISR clear the interrupts only for those channels which have interrupt enabled. The channels which are allocated for the purpose of being polled on by the accelerator will not have a callback function provided and so will not have IER (interrupt enable register) bits set. Tested on DM365 and OMAP-L137/L138 with audio and MMC/SD (as EDMA users). Signed-off-by: NAnuj Aggarwal <anuj.aggarwal@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> CC: Archith John Bency <archith@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Vipin Bhandari 提交于
The merge for 2.6.34 brings in 8-bit support to the DaVinci MMC/SD driver. This patch updates the platform data for DA830/OMAP-L137 EVM to use 8-wire support available in the driver. Signed-off-by: NVipin Bhandari <vipin.bhandari@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Vipin Bhandari 提交于
The DA830/OMAP-L137 EVM has GPIO based card detection logic, but the current code does not use it. Add support for GPIO based card detection to avoid reading the card to see if a card is present or not. Signed-off-by: NVipin Bhandari <vipin.bhandari@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Kevin Hilman 提交于
Cleanup usage of void pointers when using genirq. genirq API takes and returns void *, where this GPIO API is using those as __iomem pointers. Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Kevin Hilman 提交于
- Convert data/functions to static - include headers for missing declarations - pointer cleanups: struct foo *__iomem f --> struct foo __iomem *f; Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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- 08 4月, 2010 1 次提交
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由 Sergei Shtylyov 提交于
This hushes the following warning: arch/arm/mach-davinci/include/mach/da8xx.h:104: warning: ‘struct platform_device’ declared inside parameter list arch/arm/mach-davinci/include/mach/da8xx.h:104: warning: its scope is only this definition or declaration, which is probably not what you want Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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- 06 4月, 2010 4 次提交
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由 Kevin Hilman 提交于
IRQ 29 has two possible interrupts DDRINT and RTC, but having both in the default priority table is confusing (and triggers a warning from sparse.) This patch removes the lower priority DDRINT from the default priority table leaving the RTC setting as the default. Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Brian Niebuhr 提交于
This patch fixes an issue where a DMA channel can erroneously process an event generated by a previous transfer. A failure case is where DMA is being used for SPI transmit and receive channels on OMAP L138. In this case there is a single bit that controls all event generation from the SPI peripheral. Therefore it is possible that between when edma_stop() has been called for the transmit channel on a previous transfer and edma_start() is called for the transmit channel on a subsequent transfer, that a transmit event has been generated. The fix is to clear events in edma_start(). This prevents false events from being processed when events are enabled for that channel. Signed-off-by: NBrian Niebuhr <bniebuhr@efjohnson.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
The da8xx/omap-l1 boards refuse to build when CONFIG_DAVINCI_MUX is undefined because arch/arm/mach-davinci/mux.c:da8xx_pinmux_setup() is not defined. This patch fixes this issue. This is build tested with davinci_all_defconfig and da8xx_omapl_defconfig and boot tested on DA830 EVM. Reported-by: NShanmuga Sundaram Mahendran <shanmuga@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Kevin Hilman 提交于
On da830, when the same timer is used for clocksource and clockevent, the timer can be started before the clockevent is registered/initialzed. This creates a window where a timer interrupt might fire before the clockevent handler has been setup and causes a crash. This patch moves the actual enable/start of the timer after the clockevent has ben registered. Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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- 30 3月, 2010 1 次提交
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由 Tejun Heo 提交于
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: NTejun Heo <tj@kernel.org> Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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- 02 3月, 2010 2 次提交
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由 Sandeep Paulraj 提交于
The DM365 Spectrum Digital EVM comes with an EEPROM connected to SPI0. This patch adds support for the SPI EEPROM. Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sandeep Paulraj 提交于
This patch adds SPI init for DM365. It does the following 1) Initializes SPI0 2) Defines resources to be used by SPI0 3) Adds platform data for SPI0 Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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