1. 07 1月, 2011 1 次提交
  2. 03 1月, 2011 1 次提交
  3. 19 9月, 2010 1 次提交
  4. 08 9月, 2010 1 次提交
    • R
      ARM: Ensure PTE modifications via dma_alloc_coherent are visible · 2be23c47
      Russell King 提交于
      Dave Hylands reports:
      | We've observed a problem with dma_alloc_writecombine when the system
      | is under heavy load (heavy bus traffic).  We've managed to reduce the
      | problem to the following snippet, which is run from a kthread in a
      | continuous loop:
      |
      |   void *virtAddr;
      |   dma_addr_t physAddr;
      |   unsigned int numBytes = 256;
      |
      |   for (;;) {
      |       virtAddr = dma_alloc_writecombine(NULL,
      |             numBytes, &physAddr, GFP_KERNEL);
      |       if (virtAddr == NULL) {
      |          printk(KERN_ERR "Running out of memory\n");
      |          break;
      |       }
      |
      |       /* access DMA memory allocated */
      |       tmp = virtAddr;
      |       *tmp = 0x77;
      |
      |       /* free DMA memory */
      |       dma_free_writecombine(NULL,
      |             numBytes, virtAddr, physAddr);
      |
      |         ...sleep here...
      |     }
      |
      | By itself, the code will run forever with no issues. However, as we
      | increase our bus traffic (typically using DMA) then the *tmp = 0x77
      | line will eventually cause a page fault. If we add a small delay (a
      | few microseconds) before the *tmp = 0x77, then we don't see a page
      | fault, even under heavy load.
      
      A dsb() is required after modifying the PTE entries to ensure that they
      will always be visible.  Add this dsb().
      Reported-by: NDave Hylands <dhylands@gmail.com>
      Tested-by: NDave Hylands <dhylands@gmail.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      2be23c47
  5. 27 7月, 2010 1 次提交
    • R
      ARM: DMA coherent allocator: align remapped addresses · 5bc23d32
      Russell King 提交于
      The DMA coherent remap area is used to provide an uncached mapping
      of memory for coherency with DMA engines.  Currently, we look for
      any free hole which our allocation will fit in with page alignment.
      
      However, this can lead to fragmentation of the area, and allows small
      allocations to cross L1 entry boundaries.  This is undesirable as we
      want to move towards allocating sections of memory.
      
      Align allocations according to the size, limiting the alignment between
      the page and section sizes.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      5bc23d32
  6. 01 7月, 2010 1 次提交
  7. 14 4月, 2010 1 次提交
    • N
      ARM: 6007/1: fix highmem with VIPT cache and DMA · 7e5a69e8
      Nicolas Pitre 提交于
      The VIVT cache of a highmem page is always flushed before the page
      is unmapped.  This cache flush is explicit through flush_cache_kmaps()
      in flush_all_zero_pkmaps(), or through __cpuc_flush_dcache_area() in
      kunmap_atomic().  There is also an implicit flush of those highmem pages
      that were part of a process that just terminated making those pages free
      as the whole VIVT cache has to be flushed on every task switch. Hence
      unmapped highmem pages need no cache maintenance in that case.
      
      However unmapped pages may still be cached with a VIPT cache because the
      cache is tagged with physical addresses.  There is no need for a whole
      cache flush during task switching for that reason, and despite the
      explicit cache flushes in flush_all_zero_pkmaps() and kunmap_atomic(),
      some highmem pages that were mapped in user space end up still cached
      even when they become unmapped.
      
      So, we do have to perform cache maintenance on those unmapped highmem
      pages in the context of DMA when using a VIPT cache.  Unfortunately,
      it is not possible to perform that cache maintenance using physical
      addresses as all the L1 cache maintenance coprocessor functions accept
      virtual addresses only.  Therefore we have no choice but to set up a
      temporary virtual mapping for that purpose.
      
      And of course the explicit cache flushing when unmapping a highmem page
      on a system with a VIPT cache now can go, which should increase
      performance.
      
      While at it, because the code in __flush_dcache_page() has to be modified
      anyway, let's also make sure the mapped highmem pages are pinned with
      kmap_high_get() for the duration of the cache maintenance operation.
      Because kunmap() does unmap highmem pages lazily, it was reported by
      Gary King <GKing@nvidia.com> that those pages ended up being unmapped
      during cache maintenance on SMP causing segmentation faults.
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7e5a69e8
  8. 30 3月, 2010 1 次提交
    • T
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking... · 5a0e3ad6
      Tejun Heo 提交于
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
      
      percpu.h is included by sched.h and module.h and thus ends up being
      included when building most .c files.  percpu.h includes slab.h which
      in turn includes gfp.h making everything defined by the two files
      universally available and complicating inclusion dependencies.
      
      percpu.h -> slab.h dependency is about to be removed.  Prepare for
      this change by updating users of gfp and slab facilities include those
      headers directly instead of assuming availability.  As this conversion
      needs to touch large number of source files, the following script is
      used as the basis of conversion.
      
        http://userweb.kernel.org/~tj/misc/slabh-sweep.py
      
      The script does the followings.
      
      * Scan files for gfp and slab usages and update includes such that
        only the necessary includes are there.  ie. if only gfp is used,
        gfp.h, if slab is used, slab.h.
      
      * When the script inserts a new include, it looks at the include
        blocks and try to put the new include such that its order conforms
        to its surrounding.  It's put in the include block which contains
        core kernel includes, in the same order that the rest are ordered -
        alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
        doesn't seem to be any matching order.
      
      * If the script can't find a place to put a new include (mostly
        because the file doesn't have fitting include block), it prints out
        an error message indicating which .h file needs to be added to the
        file.
      
      The conversion was done in the following steps.
      
      1. The initial automatic conversion of all .c files updated slightly
         over 4000 files, deleting around 700 includes and adding ~480 gfp.h
         and ~3000 slab.h inclusions.  The script emitted errors for ~400
         files.
      
      2. Each error was manually checked.  Some didn't need the inclusion,
         some needed manual addition while adding it to implementation .h or
         embedding .c file was more appropriate for others.  This step added
         inclusions to around 150 files.
      
      3. The script was run again and the output was compared to the edits
         from #2 to make sure no file was left behind.
      
      4. Several build tests were done and a couple of problems were fixed.
         e.g. lib/decompress_*.c used malloc/free() wrappers around slab
         APIs requiring slab.h to be added manually.
      
      5. The script was run on all .h files but without automatically
         editing them as sprinkling gfp.h and slab.h inclusions around .h
         files could easily lead to inclusion dependency hell.  Most gfp.h
         inclusion directives were ignored as stuff from gfp.h was usually
         wildly available and often used in preprocessor macros.  Each
         slab.h inclusion directive was examined and added manually as
         necessary.
      
      6. percpu.h was updated not to include slab.h.
      
      7. Build test were done on the following configurations and failures
         were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
         distributed build env didn't work with gcov compiles) and a few
         more options had to be turned off depending on archs to make things
         build (like ipr on powerpc/64 which failed due to missing writeq).
      
         * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
         * powerpc and powerpc64 SMP allmodconfig
         * sparc and sparc64 SMP allmodconfig
         * ia64 SMP allmodconfig
         * s390 SMP allmodconfig
         * alpha SMP allmodconfig
         * um on x86_64 SMP allmodconfig
      
      8. percpu.h modifications were reverted so that it could be applied as
         a separate patch and serve as bisection point.
      
      Given the fact that I had only a couple of failures from tests on step
      6, I'm fairly confident about the coverage of this conversion patch.
      If there is a breakage, it's likely to be something in one of the arch
      headers which should be easily discoverable easily on most builds of
      the specific arch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
      5a0e3ad6
  9. 16 2月, 2010 1 次提交
  10. 15 2月, 2010 6 次提交
  11. 25 11月, 2009 10 次提交
  12. 26 10月, 2009 1 次提交
  13. 24 7月, 2009 1 次提交
  14. 16 3月, 2009 1 次提交
    • N
      [ARM] introduce dma_cache_maint_page() · 43377453
      Nicolas Pitre 提交于
      This is a helper to be used by the DMA mapping API to handle cache
      maintenance for memory identified by a page structure instead of a
      virtual address.  Those pages may or may not be highmem pages, and
      when they're highmem pages, they may or may not be virtually mapped.
      When they're not mapped then there is no L1 cache to worry about. But
      even in that case the L2 cache must be processed since unmapped highmem
      pages can still be L2 cached.
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      43377453
  15. 13 3月, 2009 1 次提交
    • R
      [ARM] Fix virtual to physical translation macro corner cases · 1522ac3e
      Russell King 提交于
      The current use of these macros works well when the conversion is
      entirely linear.  In this case, we can be assured that the following
      holds true:
      
      	__va(p + s) - s = __va(p)
      
      However, this is not always the case, especially when there is a
      non-linear conversion (eg, when there is a 3.5GB hole in memory.)
      In this case, if 's' is the size of the region (eg, PAGE_SIZE) and
      'p' is the final page, the above is most definitely not true.
      
      So, we must ensure that __va() and __pa() are only used with valid
      kernel direct mapped RAM addresses.  This patch tweaks the code
      to achieve this.
      Tested-by: NCharles Moschel <fred99@carolina.rr.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      1522ac3e
  16. 08 1月, 2009 1 次提交
    • D
      NOMMU: Rename ARM's struct vm_region · 9c93af1e
      David Howells 提交于
      Rename ARM's struct vm_region so that I can introduce my own global version
      for NOMMU.  It's feasible that the ARM version may wish to use my global one
      instead.
      
      The NOMMU vm_region struct defines areas of the physical memory map that are
      under mmap.  This may include chunks of RAM or regions of memory mapped
      devices, such as flash.  It is also used to retain copies of file content so
      that shareable private memory mappings of files can be made.  As such, it may
      be compatible with what is described in the banner comment for ARM's vm_region
      struct.
      Signed-off-by: NDavid Howells <dhowells@redhat.com>
      9c93af1e
  17. 30 9月, 2008 1 次提交
  18. 29 9月, 2008 1 次提交
  19. 26 9月, 2008 2 次提交
  20. 25 9月, 2008 1 次提交
  21. 19 7月, 2008 1 次提交
  22. 11 11月, 2007 1 次提交
  23. 13 10月, 2007 1 次提交
  24. 08 2月, 2007 2 次提交