- 17 7月, 2014 1 次提交
-
-
由 Thierry Reding 提交于
In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
- 09 6月, 2014 10 次提交
-
-
由 Thierry Reding 提交于
According to the DP specification the disparity of the first symbol should always be negative. It is therefore safe to assume that panels will conform to that and therefore parameterizing this field should never be necessary. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
Instead of always enabling all four lanes, enable only the number probed from the link. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
Power on only those lanes required for the specified link. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
Interlaced mode is currently not supported on the SOR, so don't program any associated registers. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
Use the speed probed from the link at runtime rather than relying on a hardcoded default. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
The number of HBLANK and VBLANK symbols can be computed at runtime so that they can be set appropriately depending on the video mode and DP link. These values are used by the packet generation logic to determine how many audio samples can be transferred during the blanking intervals. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
The currently hardcoded link parameters don't work on all eDP panels, so compute the parameters at runtime depending on the mode and panel type to allow the driver to cope with a wider variety of panels. Note that the number of bits per pixel of the panel is still hardcoded, but this can be addressed in a separate patch. This is largely based on a patch by Stéphane Marchesin but the algorithm was largely rewritten to be more readable and concise. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Stéphane Marchesin 提交于
Lanes are powered up in decreasing order. Power them down in increasing order for consistency. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Stéphane Marchesin 提交于
The comment above mentions link A/B but this isn't what the code does, so let's fix that. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Stéphane Marchesin 提交于
The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: NStéphane Marchesin <marcheu@chromium.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
-
- 06 6月, 2014 6 次提交
-
-
由 Thierry Reding 提交于
Other output drivers set up debugfs slightly differently. Bring the SOR driver in line with those for consistency. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
Removing only the root directory will fail when there are still files in it. Instead of manually removing all files, remove the whole directory recursively. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
The DRM core can now cope with drivers that don't have an associated struct drm_bus, so the host1x implementation is no longer useful. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
Accessing the CRC debugfs file will hang the system if the SOR is not enabled, so make sure that it is stays enabled until the CRC has been read. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
The shift clock divider is highly dependent on the type of output, so push computation of it down into the output drivers. The old code used to work merely by accident. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
由 Thierry Reding 提交于
The SOR allows the computation of a 32 bit CRC of the content that it transmits. This functionality is exposed via debugfs and is useful to verify proper operation of the SOR. Signed-off-by: NThierry Reding <treding@nvidia.com>
-
- 04 4月, 2014 1 次提交
-
-
由 Thierry Reding 提交于
Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: NThierry Reding <treding@nvidia.com>
-