1. 23 9月, 2015 9 次提交
    • S
      drm/i915: Check live status before reading edid · 237ed86c
      Sonika Jindal 提交于
      The Bspec is very clear that Live status must be checked about before
      trying to read EDID over DDC channel. This patch makes sure that HDMI
      EDID is read only when live status is up.
      
      The live status doesn't seem to perform very consistent across various
      platforms when tested with different monitors. The reason behind that is
      some monitors are late to provide right voltage to set live_status up.
      So, after getting the interrupt, for a small duration, live status reg
      fluctuates, and then settles down showing the correct staus.
      
      This is explained here in, in a rough way:
      HPD line  ________________
      			 |\ T1 = Monitor Hotplug causing IRQ
      			 | \______________________________________
      			 | |
                               | |
      			 | |   T2 = Live status is stable
      			 | |  _____________________________________
      			 | | /|
      Live status _____________|_|/ |
      			 | |  |
      			 | |  |
      			 | |  |
      			T0 T1  T2
      
      (Between T1 and T2 Live status fluctuates or can be even low, depending on
       the monitor)
      
      After several experiments, we have concluded that a max delay
      of 30ms is enough to allow the live status to settle down with
      most of the monitors. This total delay of 30ms has been split into
      a resolution of 3 retries of 10ms each, for the better cases.
      
      This delay is kept at 30ms, keeping in consideration that, HDCP compliance
      expect the HPD handler to respond a plug out in 100ms, by disabling port.
      
      v2: Adding checks for VLV/CHV as well. Reusing old ibx and g4x functions
      to check digital port status. Adding a separate function to get bxt live
      status (Daniel)
      v3: Using intel_encoder->hpd_pin to check the live status (Siva)
      Moving the live status read to intel_hdmi_probe and passing parameter
      to read/not to read the edid. (me)
      v4:
      * Added live status check for all platforms using
      intel_digital_port_connected.
      * Rebased on top of Jani's DP cleanup series
      * Some monitors take time in setting the live status. So retry for few
      times if this is a connect HPD
      v5: Removed extra "drm/i915" from commit message. Adding Shashank's sob
          which was missed.
      v6: Drop the (!detect_edid && !live_status check) check because for DDI
      ports which are enumerated as hdmi as well as DP, we don't have a
      mechanism to differentiate between DP and hdmi inside the encoder's
      hot_plug. This leads to call to the hdmi's hot_plug hook for DP as well
      as hdmi which leads to issues during unplug because of the above check.
      v7: Make intel_digital_port_connected global in this patch, some
      reformatting of while loop, adding a print when live status is not
      up. (Rodrigo)
      v8: Rebase it on nightly which involved skipping the hot_plug hook for now
      and letting the live_status check happen in detect until the hpd handling
      part is finalized (Daniel)
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Signed-off-by: NSonika Jindal <sonika.jindal@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      237ed86c
    • S
      drm/i915/bxt: DSI prepare changes for BXT · d2e08c0f
      Shashank Sharma 提交于
      This patch modifies dsi_prepare() function to support the same
      modeset prepare sequence for BXT also. Main changes are:
      1. BXT port control register is different than VLV.
      2. BXT modeset sequence needs vdisplay and hdisplay programmed
         for transcoder.
      3. BXT can select PIPE for MIPI transcoders.
      4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
         even if only one is being used.
      
      v2: Fixed Jani's review comments. Rectified the DSI Macros to get
          proper register offsets using _MIPI_PORT instead of _TRANSCODER
      
      v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Signed-off-by: NUma Shankar <uma.shankar@intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d2e08c0f
    • S
      drm/i915/bxt: Disable DSI PLL for BXT · fe88fc68
      Shashank Sharma 提交于
      This patch adds two new functions:
      - disable_dsi_pll.
        BXT DSI disable sequence and registers are
        different from previous platforms.
      - intel_disable_dsi_pll
        wrapper function to re-use the same code for
        multiple platforms. It checks platform type and
        calls appropriate core pll disable function.
      
      v2: Fixed Jani's review comments.
      
      v3: Rebased on latest drm-nightly branch.
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Signed-off-by: NUma Shankar <uma.shankar@intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      fe88fc68
    • S
      drm/i915/bxt: Enable BXT DSI PLL · cfe01a5e
      Shashank Sharma 提交于
      This patch adds new functions for BXT clock and PLL programming.
      They are:
      1. configure_dsi_pll for BXT.
         This function does the basic math and generates the divider ratio
         based on requested pixclock, and program clock registers.
      2. enable_dsi_pll function.
         This function programs the calculated clock values on the PLL.
      3. intel_enable_dsi_pll
         Wrapper function to use same code for multiple platforms. It checks the
         platform and calls appropriate core pll enable function.
      
      v2: Fixed Jani's review comments. Macros are adjusted as per convention.
      
      v3: Removed a redundant change wrt code comment.
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Signed-off-by: NUma Shankar <uma.shankar@intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      cfe01a5e
    • S
      drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack · 83e33372
      Sagar Arun Kamble 提交于
      On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
      [drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
      Polling for 50ms is recommended to avoid these timeouts.
      
      Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Reviewed by: Alex Dai <yu.dai@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      83e33372
    • S
      drm/i915/bxt: WaGsvDisableTurbo · 23eafea6
      Sagar Arun Kamble 提交于
      Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
      
      Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Reviewed by: Alex Dai <yu.dai@intel.com>.
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      23eafea6
    • A
      drm/i915/bxt: Modified HAS_CSR, added support for BXT · 7b403ffb
      Animesh Manna 提交于
      Modified HAS_CSR macro defination which earlier only supported
      for skl, now added support for BXT.
      
      v1: Initial version.
      
      v2: Instaed of skylake/broxton check added gen9 check alone based
      on review comment from Sunil.
      
      Cc: Vetter, Daniel <daniel.vetter@intel.com>
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Cc: Imre Deak <imre.deak@intel.com>
      Cc: Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: NAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      7b403ffb
    • A
      drm/i915/bxt: Stepping info added for bxt. · cff765fb
      Animesh Manna 提交于
      Added stepping info in intel_csr.c which is required to extract
      specific firmware from packaged dmc firmware.
      
      Stepping info is aligned with current bspec info.
      
      Cc: Vetter, Daniel <daniel.vetter@intel.com>
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Cc: Imre Deak <imre.deak@intel.com>
      Cc: Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: NAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      cff765fb
    • A
      drm/i915/bxt: Path added of dmc firmware ver1 for BXT. · 18c237c0
      Animesh Manna 提交于
      Broxton also has dmc to manage low-power display engine state.
      Path of the firmware added in intel_csr.c.
      
      Naming convention followed as <platform>_dmc_<api-version>.bin
      
      v1: Initial version.
      
      v2: Commit description added based on review comment from Sunil.
      
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: NAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      18c237c0
  2. 22 9月, 2015 5 次提交
  3. 21 9月, 2015 1 次提交
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  6. 15 9月, 2015 1 次提交
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  9. 11 9月, 2015 1 次提交