1. 25 6月, 2013 1 次提交
    • D
      ASoC: adau1701: allow configuration of PLL mode pins · 2352d4bf
      Daniel Mack 提交于
      The ADAU1701 has 2 hardware pins to configure the PLL mode in accordance
      to the MCLK-to-LRCLK ratio. These pins have to be stable before the chip
      is released from reset, and a full reset cycle, including a new firmware
      download is needed whenever they change.
      
      This patch adds GPIO properties to the DT bindings of the Codec, and
      implements makes the set_sysclk memorize the configured sysclk.
      
      Because the run-time parameters are unknown at probe time, the first
      firmware download is postponed to the first hw_params call, when the
      driver can determine the mclk/lrclk divider. Subsequent downloads
      are only issued when the divider configuration changes.
      Signed-off-by: NDaniel Mack <zonque@gmail.com>
      Acked-by: NLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      2352d4bf
  2. 25 5月, 2013 1 次提交
  3. 08 5月, 2013 2 次提交
  4. 30 4月, 2013 9 次提交
  5. 29 4月, 2013 1 次提交
  6. 28 4月, 2013 1 次提交
  7. 26 4月, 2013 3 次提交
  8. 25 4月, 2013 2 次提交
  9. 24 4月, 2013 3 次提交
  10. 20 4月, 2013 1 次提交
    • A
      ata: arasan: remove the need for platform_data · e34d3865
      Arnd Bergmann 提交于
      This adds a complete DT binding for the arasan device driver. There is
      currently only one user, which is the spear13xx platform, so we don't
      actually have to parse all the properties until another user comes in,
      but this does use the generic DMA binding to find the DMA channel.
      
      The patch is untested so far and is part of a series to convert
      the spear platform over to use the generic DMA binding, so it
      should stay with the rest of the series.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Acked-by: NViresh Kumar <viresh.linux@linaro.org>
      Cc: Vinod Koul <vinod.koul@intel.com>
      Cc: Jeff Garzik <jgarzik@redhat.com>
      Cc: devicetree-discuss@lists.ozlabs.org
      e34d3865
  11. 19 4月, 2013 1 次提交
  12. 18 4月, 2013 1 次提交
  13. 17 4月, 2013 2 次提交
  14. 16 4月, 2013 5 次提交
  15. 15 4月, 2013 1 次提交
    • D
      ARM: socfpga: Add clock entries into device tree · 042000b0
      Dinh Nguyen 提交于
      Adds the main PLL clock groups for SOCFPGA into device tree file
      so that the clock framework to query the clock and clock rates
      appropriately.
      
      $cat /sys/kernel/debug/clk/clk_summary
         clock                        enable_cnt  prepare_cnt  rate
      ---------------------------------------------------------------------
       osc1                           2           2            25000000
          sdram_pll                   0           0            400000000
             s2f_usr2_clk             0           0            66666666
             ddr_dq_clk               0           0            200000000
             ddr_2x_dqs_clk           0           0            400000000
             ddr_dqs_clk              0           0            200000000
          periph_pll                  2           2            500000000
             s2f_usr1_clk             0           0            50000000
             per_base_clk             4           4            100000000
             per_nand_mmc_clk         0           0            25000000
             per_qsi_clk              0           0            250000000
             emac1_clk                1           1            125000000
             emac0_clk                0           0            125000000
          main_pll                    1           1            1600000000
             cfg_s2f_usr0_clk         0           0            100000000
             main_nand_sdmmc_clk      0           0            100000000
             main_qspi_clk            0           0            400000000
             dbg_base_clk             0           0            400000000
             mainclk                  0           0            400000000
             mpuclk                   1           1            800000000
                smp_twd               1           1            200000000
      Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
      Reviewed-by: NPavel Machek <pavel@denx.de>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      042000b0
  16. 13 4月, 2013 4 次提交
  17. 12 4月, 2013 2 次提交