- 05 8月, 2013 1 次提交
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由 Arnaud Ebalard 提交于
All hardware parts of the (Armada 370 based) NETGEAR ReadyNAS 102 are supported by mainline kernel (USB 3.0 rear ports, USB 2.0 front port, Gigabit controller and PHY, serial port, leds, buttons, SATA ports, G762 fan controller) except for: - the Intersil ISL12057 I2C RTC Chip, - the Armada NAND controller. Support for both of those is currently work in progress and does not prevent boot. Signed-off-by: NArnaud Ebalard <arno@natisbad.org> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 26 7月, 2013 1 次提交
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由 Arnaud Ebalard 提交于
Now that GMT G762 PWM Fan Controller is available upstream, let's add missing bindings in Netgear ReadyNAS Duo v2 .dts file. Signed-off-by: NArnaud Ebalard <arno@natisbad.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 10 7月, 2013 1 次提交
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由 Kyungsik Lee 提交于
Integrates the LZ4 decompression code to the arm pre-boot code. Signed-off-by: NKyungsik Lee <kyungsik.lee@lge.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Borislav Petkov <bp@alien8.de> Cc: Florian Fainelli <florian@openwrt.org> Cc: Yann Collet <yann.collet.73@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 04 7月, 2013 1 次提交
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由 Xianglong Du 提交于
On CSR SiRFprimaII/atlasVI, there is a programmable 16-bit divider (RTC_DIV) that divides the input 32.768KHz clock to the frequency that users need (E.g. 1 Hz). The divided real-time clock will be used to drive a 32-bit counter (RTC_COUNTER) that provides users with the actual time. In each cycle of the divided real-time clock, there is a Hertz interrupt generated to the RISC. Users can also configure an alarm (RTC_ALARM). When RTC_COUNTER matches the alarm, there will be an alarm interrupt generated to the RISC. The system RTC can generate an alarm wake-up signal to notify the power controller to wake up from power saving mode. Signed-off-by: NXianglong Du <Xianglong.Du@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Cc: Jingoo Han <jg1.han@samsung.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 03 7月, 2013 1 次提交
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由 Stephen Warren 提交于
Commit 4c94c8b5 "ARM: tegra: update device trees for USB binding rework" added regulator definitions for GPIO-controlled USB VBUS. However, none of these contained the essential DT property enable-active-high. Add this so that the regulator definitions are correct. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 28 6月, 2013 2 次提交
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由 Rahul Sharma 提交于
This patch renames the combatible strings for hdmi, mixer, ddc and hdmiphy. It follows the convention of using compatible string which represent the SoC in which the IP was added for the first time. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NInki Dae <inki.dae@samsung.com>
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由 Geert Uytterhoeven 提交于
Several drivers need font support independent of CONFIG_VT, cfr. commit 9cbce8d7e1dae0744ca4f68d62aa7de18196b6f4, "console/font: Refactor font support code selection logic"). Hence move the fonts and their support logic from drivers/video/console/ to its own library directory lib/fonts/. This also allows to limit processing of drivers/video/console/Makefile to CONFIG_VT=y again. [Kevin Hilman <khilman@linaro.org>: Update arch/arm/boot/compressed/Makefile] Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
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- 27 6月, 2013 5 次提交
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由 Fabio Estevam 提交于
Instead of using a GPIO to turn on/off the CAN transceiver, it is better to use a regulator as some systems may use a PMIC to power the CAN transceiver. Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Linus Walleij 提交于
This alters the local side address of the iospace to zero, non prefetchable memory local side address to 0x00000000 and prefetchable memory local side address to 0x10000000, so as to match the values actually poked in by the driver. Reported-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Manjunathappa, Prakash 提交于
function-mask DT property is now a mask for a pin at each pin offset inside a given pincontrol register. Fix DA850 DT data to reflect this change. Signed-off-by: NManjunathappa, Prakash <prakash.pm@ti.com> [nsekhar@ti.com: reword commit message for clarity] Signed-off-by: NSekhar Nori <nsekhar@ti.com>
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由 Jingoo Han 提交于
This patch adds pcie controller node for exynos5440-ssdk5440, and also adds a phandle for pin controller node. Signed-off-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Jingoo Han 提交于
Exynos5440 has two PCIe controllers which can be used as root complex for PCIe interface. Signed-off-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 26 6月, 2013 9 次提交
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Nicolas Ferre 提交于
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Nicolas Ferre 提交于
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NWenyou Yang <wenyou.yang@atmel.com>
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由 Nicolas Ferre 提交于
In previous version of SPI driver we where using different compatibility stings for finding SPI features. We are now using the IP revision information. So we stay with the unique compatibility string for this driver: "atmel,at91rm9200-spi". Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NWenyou Yang <wenyou.yang@atmel.com>
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由 Srinivas Kandagatla 提交于
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with standard set-top box IPs. This patch adds initial support to B2020 with STiH415/416 with SBC_UART1 as console and a heard beat LED. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Srinivas Kandagatla 提交于
B2000 board is reference board for STIH415/416 SOCs, it has 2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM. This patch add initial support to b2000 with STiH415/416 with UART2 as console and a heard beat LED. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Arnd Bergmann <arnd@arndb.de> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Srinivas Kandagatla 提交于
The STiH416 is advanced HD AVC processor with 3D graphics acceleration and 1.2-GHz ARM Cortex-A9 SMP CPU. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Srinivas Kandagatla 提交于
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 24 6月, 2013 2 次提交
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由 Marc Zyngier 提交于
arm26 support in Linux is long gone, yet it left an interresting, fossilized trace in the decompressor. Remove it so people won't get confused about what teqp is actually doing here... Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Ezequiel Garcia 提交于
The length of the registers area for the Marvell 370/XP Ethernet controller was incorrect in the .dtsi: 0x2500, while it should have been 0x4000. This problem wasn't noticed because there used to be a static mapping for all the MMIO register region set up by ->map_io(). The register length was fixed in all the other device tree files, except from the armada-xp-mv78260.dtsi, in the following commit: commit cf8088c5 Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue May 21 12:33:27 2013 +0200 arm: mvebu: fix length of Ethernet registers area in .dtsi This commit fixes a kernel panic in mvneta_probe(), when the kernel tries to access the unmapped registers: [ 163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e [ 163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef [ 163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c [ 163.661258] Unable to handle kernel paging request at virtual address f011bcf0 [ 163.668523] pgd = c0004000 [ 163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000 [ 163.677565] Internal error: Oops: 807 [#1] SMP ARM [ 163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11 [ 163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000 [ 163.695467] PC is at mvneta_probe+0x34c/0xabc [...] Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 22 6月, 2013 1 次提交
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由 Daniel Tang 提交于
This patch adds device trees for describing the TI-Nspire hardware. Changes between v1 and v2: * Change "keymap" binding to the standard "linux,keymap" binding. Signed-off-by: NDaniel Tang <dt.tangr@gmail.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 21 6月, 2013 7 次提交
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由 Ezequiel Garcia 提交于
Although the internal register window size is 1 MiB, the previous ranges translation for the internal register space had a size of 0x4000000. This was done to allow the crypto and nand node to access the corresponding 'sram' and 'nand' decoding windows. In order to describe the hardware more accurately, we declare the real 1 MiB internal register space in the ranges, and add a translation entry for the nand node to access the 'nand' window. This commit will make future improvements on the MBus DT binding easier. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Lee Jones 提交于
When this node was added, the AB8500 GPIO driver was pretty broken. As a hack, we pretended that NOMADIK GPIO 26 was the correct on/off pin, as it was unused. It worked because AB8500 GPIO 26 was in an 'always on from boot' state. Now the AB8500 GPIO driver is working, the default state for all the pins is 'off'. Let's flip back over to use the correct GPIO which is _actually_ attached to the regulator. We're also taking the opportunity to straighten out some formatting misdemeanours, swapping spaces for tabs. Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Lee Jones 提交于
Here we're adding a node for the AB8500 GPIO device. This will allow other DT:ed components to obtain GPIOs for use within their drivers. Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Heiko Stuebner 提交于
This adds a generic devicetree board file and a dtsi for boards based on the RK3066a SoCs from Rockchip. Apart from the generic parts (gic, clocks, pinctrl) the only components currently supported are the timers, uarts and mmc ports (all DesignWare- based). Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Heiko Stuebner 提交于
This adds a basic clock setup for rk3066a SoCs. Only the gates are set up currently, as the mux and dividers should use the upcoming generic devicetree bindings. Clocks whose rates need to be known are supplied by fixed-rate "dummy"-clocks that provide the correct rate. This is uncritical insofar that the only bootloader currently in existence for Rockchip devices is the propietary Rockchip one that always setups the clocks in the necessary way. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NMike Turquette <mturquette@linaro.org>
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由 Matt Porter 提交于
CodingStyle does not allow C99 style comments. Since the dts files live in the kernel for now, make this compliant. Signed-off-by: NMatt Porter <matt.porter@linaro.org> Acked-by: NChristian Daudt <csd@broadcom.com>
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由 Christian Daudt 提交于
Add SDHCI bindings for the Broadcom 281xx SoCs. Changes from V2: - Documentation cleanups Changes from V1: - split original patch into 2, one for driver and this one for dt Signed-off-by: NChristian Daudt <csd@broadcom.com> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 20 6月, 2013 5 次提交
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由 Philip Avinash 提交于
Replace /include/ by #include for da850 device tree files, in order to use the C pre-processor, making use of #define features possible. Signed-off-by: NPhilip Avinash <avinashphilip@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com>
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由 Linus Walleij 提交于
This revamps the device tree to fit with the new clock implementation and brings it quite a bit closer to how the hardware actually works. After this the clock implementation knows about all clock gates and will gate off all unused clocks at boot time and save a bit of power. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Roger Quadros 提交于
USB Host PHY clock on port 2 must be configured to 19.2MHz. Provide this information. Cc: Sricharan R <r.sricharan@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Roger Quadros 提交于
On Panda the +5V supply for DVI EDID is supplied by the same regulator that poweres the USB Hub. Currently, the DSS/DVI subsystem doesn't know how to manage this regulator and so DVI EDID reads will fail if USB Hub is not enabled. As a temporary fix we keep this regulator permanently enabled on boot. This fixes the DVI EDID read problem. CC: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Roger Quadros 提交于
Provide the RESET and Power regulators for the USB PHY, the USB Host port mode and the PHY device. Also provide pin multiplexer information for the USB host pins. HACK: The reset control need to be replaced with the proper gpio-controlled reset driver as soon it will be merged [1]. [1] http://thread.gmane.org/gmane.linux.drivers.devicetree/36830Signed-off-by: NRoger Quadros <rogerq@ti.com> [benoit.cousson@linaro.org: Add disclaimer about the reset control inside changelog and code] Cc: Florian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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- 19 6月, 2013 4 次提交
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由 Thomas Petazzoni 提交于
The Armada 370 RD board has two internal mini-PCIe connectors. This commit adds the necessary Device Tree informations to enable the usage of those mini-PCIe connectors. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Florian Fainelli <florian@openwrt.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Leela Krishna Amudala 提交于
Add the required pin configuration support to EXYNOS5420 using pinctrl interface. Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Acked-by: NTomasz Figa <t.figa@samsung.com> Tested-by : Sunil Joshi <joshi@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Afzal Mohammed 提交于
Add AM43x ePOS EVM minimal DT source - this is a minimal one to get it booting. Also include it in omap2plus dtbs and document bindings. The hardware is under development. Signed-off-by: NAfzal Mohammed <afzal@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Eduardo Valentin 提交于
Add bandgap device DT entry for OMAP5 dtsi. Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: NJ Keerthy <j-keerthy@ti.com> [benoit.cousson@linaro.org: Fix alignement and use the macros for IRQ attributes] Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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