After commit 81b34fbe ("OMAP2 clock:
split OMAP2420, OMAP2430 clock data into their own files"), it's
possible to remove dsp_irate_ick from the OMAP2420 and OMAP2430 clock
files.  It was originally only needed due to a 2420/2430 clock tree difference,
and now that the data is in separate files, it's superfluous.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Remove the DPLL rate tolerance code that is called during rate
rounding.  As far as I know, this code is never used, since it's been
more important for callers of the DPLL round_rate()/set_rate()
functions to obtain an exact rate than it is to save a relatively
small amount of power.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Bail out before we take the clockfw_lock spinlock if the corresponding
OMAP1 or OMAP2+ clock function is not defined.  The intention is to
reduce and simplify the work that is done inside the spinlock.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck.  This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.

So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.

Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The OMAP2420/2430 external 32-kHz low-frequency oscillator is a 32768
Hz oscillator, not a 32,000 Hz oscillator[1][2].  Fix this in the clock
tree.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

1. OMAP2420/22 Multimedia Processor Data Manual, Version P [SWPS019P],
   section 5.1.4 "External 32-kHz CMOS Clock" (note that it refers to
   a "32.768-kHz" clock; this presumably should be "32.768-KHz")

2. OMAP2430 Multimedia Processor ES2.1 Data Manual, Version V [SWPS023V],
   section 5.1.4 "External 32-kHz CMOS Clock" (note that it refers to
   a "32.768-kHz" clock; this presumably should be "32.768-KHz")

Several clocks are listed as having the core L4 clock as their parent,
when they are actually derived from the L3 clock.  Fix these.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

These CM_AUTOIDLE bits are now set by the clock code via the common PM
code in mach-omap2/pm.c.

N.B.: The pm24xx.c code that this patch removes didn't ensure that the
CM_AUTOIDLE bits were set for several 2430-only modules, such as
GPIO5, MDM_INTC, MMCHS1/2, the modem oscillator clock, and USBHS.
Similarly, the pm34xx.c code that this patch removes didn't ensure
that the CM_AUTOIDLE bits were set for USIM and the AM3517 UART4.
Those cases should now be handled.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

OMAP2430 and OMAP3xxx have modem autoidle bits that are actually
attached to clocks with CM_FCLKEN bits; add the code and data to
handle these.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Add sdrc_ick to the OMAP2420 clock data so the clock code can control
the CM_AUTOIDLE bit associated with this clock.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Add interface clock type code with autoidle enable/disable support.
The clkops structures created in this file will be used for all
OMAP2/3 interface clocks with autoidle support.  They will enable the
clock framework to control interface clock autoidle directly.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Place some comments in the OMAP oscillator clock control code to note that
its autoidle mode should eventually be controlled via the new OMAP clockfw
autoidle control interface.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

OMAP2xxx devices have two on-chip APLLs.  These APLLs can
automatically enter idle when not in use.  Connect the APLL autoidle
code to the clock code, so that the clock framework can handle this
process.  As part of this patch, remove the code in mach-omap2/pm24xx.c
that previously handled APLL autoidle control.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Add the necessary code and data to allow the clock framework to enable
and disable the OMAP2 DPLL autoidle state.  This is so the direct
register access can be moved out of the mach-omap2/pm24xx.c code, and other
code that needs to control this (e.g., CPUIdle) can do so via an API.
As part of this patch, remove the pm24xx.c code that formerly wrote
directly to the autoidle bits.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Disable autoidle on all clocks during clock framework initialization.
(If CONFIG_PM is set, autoidle is re-enabled for all clocks later in
the boot process.)

The principle behind this patch, and some similar patches, is that the
kernel should start with all power management features disabled.
Later in the boot process, the PM code, if compiled in with CONFIG_PM,
enables or re-enables power management features.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Enable hardware gate control for all dpll MX and X2 postdividers.
This requires the allow_idle/deny_idle functions to be
populated for all clock nodes (mx/x2 post dividers) in
clkops.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.

Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.

NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: moved OMAP4-specific DPLL control code to
 mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Attempt to enable autoidle for as many clocks as possible in the
OMAP2+-common CONFIG_OMAP_RESET_CLOCKS code.  Currently, this only
enables DPLL autoidle for OMAP3/4 DPLLs; but future patches will
enable autoidle for other clocks and the OMAP2 DPLL/APLLs.

In the long run, we should probably get rid of
CONFIG_OMAP_RESET_CLOCKS, and unconditionally run the code that it
selects.  Otherwise, the state of the clock tree won't match the
hardware state - this could result in clocks being enabled or disabled
unpredictably.

Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
the pm34xx.c/pm44xx.c code.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>

All OMAP3/4 dpll's support hardware level autogating.
Populate allow_idle/deny_idle function pointers for all
DPLL's in clkops.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_autoidle_all and
omap_clk_disable_autoidle_all) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: use spinlock rather than mutex due to race; renamed functions;
 functions now return ints]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

DPLL1 on omap3 is very similar to the rest of
the non-core dpll's.
Hence populate clkops_omap3_noncore_dpll_ops
as the clkops for it, instead of the
currently populated clkops_null.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Check if enable/disable operations are supported for a given
clock node before attempting to call them.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Define the following architecture specific funtions for omap2/3/4
.clkdm_clk_enable
.clkdm_clk_disable

Convert the platform-independent framework to call these functions.
Also rename the api's by removing the omap2_ preamble.
Hence call omap2_clkdm_k_enable as clkdm_clk_enable and
omap2_clkdm_clk_disable as clkdm_clk_disable.a

Remove unused functions (_enable/_disable_hwsup) and unsed
headers from clockdomain.c file.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Define the following architecture specific funtions for omap2/3/4
.clkdm_allow_idle
.clkdm_deny_idle

Convert the platform-independent framework to call these functions.
Also rename the api's by removing the omap2_ preamble.
Hence call omap2_clkdm_allow_idle as clkdm_allow_idle and
omap2_clkdm_deny_idle as clkdm_deny_idle.

Make the _clkdm_add_autodeps and _clkdm_del_autodeps as non-static
so they can be accessed from OMAP2/3 platform specific code.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Define the following architecture specific funtions for omap2/3/4
.clkdm_sleep
.clkdm_wakeup

Convert the platform-independent framework to call these functions.
Also rename the api's by removing the omap2_ preamble.
Hence call omap2_clkdm_wakeup as clkdm_wakeup and
omap2_clkdm_sleep as clkdm_sleep.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: fixed omap3_clkdm_clear_all_sleepdeps() and
 omap2_clkdm_clear_all_wkdeps() to test against the correct
 loop termination condition; thanks to Kevin Hilman for finding and
 helping fix]
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Define the following architecture specific funtions for omap2/3
.clkdm_add_wkdep
.clkdm_del_wkdep
.clkdm_read_wkdep
.clkdm_clear_all_wkdeps
.clkdm_add_sleepdep
.clkdm_del_sleepdep
.clkdm_read_sleepdep
.clkdm_clear_all_sleepdeps

Convert the platform-independent framework to call these functions.
With this also move the clkdm lookups for all wkdep_srcs and
sleepdep_srcs at clkdm_init.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: fixed loop termination conditions in omap*_clkdm_clear_all_*();
 thanks to Kevin Hilman for finding and helping fix those bugs; also
 avoid re-resolving clockdomains during init; abstracted out clkdm_dep walk]
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Put infrastructure in place, so arch specific func pointers
can be hooked up to the platform-independent part of the
framework.
This is in preparation of splitting the clockdomain framework into
platform-independent part (for all omaps) and platform-specific
parts.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Trivial fix to remove the unused function declaration
from the powerdomain header.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Hwmod needs database of all IPs in a system. This patch generates the hwmod
database for Display Sub System applicable for OMAP3430 and
OMAP36xx.  DSS is also considered as an IP as DISPC, RFBI and named as dss_core.
For all the IP modules in DSS, same clock is needed for enabling. Hwmod sees
DSS IPs as independent IPs, so same clock has to be repeated for .main_clk in
each IP.

This patch defines separate hwmod databases for OMAP3430ES1 and (OMAP3430ES2 and
OMAP36xx) as OMAP3430ES1 does not have IDLEST bit to poll on for dss IP, and also
the firewall regions are different between 3430es1 and later.
Reviewed-by: NKevin Hilman <khilman@ti.com>
Tested-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NSenthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Hwmod needs database of all IPs in a system. This patch generates the hwmod
database for OMAP2430 Display Sub System. Since DSS is also considered as an
IP as DISPC, RFBI, name it as dss_core.
Acked-by: NBenoit Cousson <b-cousson@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Tested-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NSenthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Hwmod needs database of all IPs in a system. This patch generates the hwmod
database for OMAP2420 Display Sub System,. Since DSS is also considered as an
IP as DISPC, RFBI, name it as dss_core.
Acked-by: NBenoit Cousson <b-cousson@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Tested-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NSenthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Since the timer1 is now started before the hwmod_init, we cannot
reset it and idle it anymore.

Add the appropriate flags to prevent the hwmod framework to do that.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

- Add a rev attribute to identify various McSPI IP version.
- Add a dev_attr structure to provide the number of chipselect
  supported by the instance.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Govindraj.R <govindraj.raja@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Cleans up all base address definitions for omap_mcspi
and adapts the device registration and driver to hwmod framework.
Changes involves:
1) Removing all base address macro defines.
2) Using omap-device layer to register device and utilizing data from
   hwmod data file for base address, dma channel number, Irq_number,
   device attribute(number of chipselect).
3) Appending base address with pdata reg_offset for omap4 boards.
   For omap4 all regs used in driver deviate with reg_offset_macros
   defined with an value of 0x100. So pass this offset through pdata
   and append the same to base address retrieved from hwmod data file
   and we are not mapping *_HL_* regs which are not used in driver.
Signed-off-by: NCharulatha V <charu@ti.com>
Signed-off-by: NGovindraj.R <govindraj.raja@ti.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Reviewed-by: NPartha Basak <p-basak2@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Update omap3 hwmod data file with McSPI info.
Signed-off-by: NCharulatha V <charu@ti.com>
Signed-off-by: NGovindraj.R <govindraj.raja@ti.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Update the 2430 hwmod data file with McSPI info.
Signed-off-by: NCharulatha V <charu@ti.com>
Signed-off-by: NGovindraj.R <govindraj.raja@ti.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Update the omap2420 hwmod data with the McSPI info.
Add a device attribute structure which will be used
for passing number of chipselects from hwmod data.
Add revision macros to be passed from rev field from
hwmod.
Signed-off-by: NCharulatha V <charu@ti.com>
Signed-off-by: NGovindraj.R <govindraj.raja@ti.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Build and register an hwspinlock platform device.

Although only OMAP4 supports the hardware spinlock module (for now),
it is still safe to run this initcall on all omaps, because hwmod lookup
will simply fail on hwspinlock-less platforms.
Signed-off-by: NSimon Que <sque@ti.com>
Signed-off-by: NHari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: NOhad Ben-Cohen <ohad@wizery.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>