1. 22 12月, 2015 1 次提交
  2. 28 10月, 2015 1 次提交
    • J
      pinctrl: tegra-xusb: Correct lane mux options · 9d4cc85d
      Jon Hunter 提交于
      The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124
      documentation implies that all functions (pcie, usb3 and sata) can be
      muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has
      been confirmed that this is not the case and the mux'ing options much more
      limited. Unfortunately, the public documentation has not been updated to
      reflect this and so detail the actual mux'ing options here by function:
      
      Function:		Lanes:
      pcie1 x2:		pcie3, pcie4
      pcie1 x4:		pcie1, pcie2, pcie3, pcie4
      pcie2 x1 (option1):	pcie0
      pcie2 x1 (option2):	pcie2
      usb3 port 0:		pcie0
      usb3 port 1 (option 1):	pcie1
      usb3 port 1 (option 2):	sata0
      sata:			sata0
      Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
      Acked-by: NStephen Warren <swarren@nvidia.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      9d4cc85d
  3. 10 6月, 2015 1 次提交
  4. 01 6月, 2015 2 次提交
  5. 22 11月, 2014 1 次提交
  6. 28 10月, 2014 1 次提交
  7. 04 9月, 2014 1 次提交
  8. 17 8月, 2014 2 次提交
  9. 11 7月, 2014 1 次提交