- 22 12月, 2015 1 次提交
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由 Julia Lawall 提交于
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 28 10月, 2015 1 次提交
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由 Jon Hunter 提交于
The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124 documentation implies that all functions (pcie, usb3 and sata) can be muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has been confirmed that this is not the case and the mux'ing options much more limited. Unfortunately, the public documentation has not been updated to reflect this and so detail the actual mux'ing options here by function: Function: Lanes: pcie1 x2: pcie3, pcie4 pcie1 x4: pcie1, pcie2, pcie3, pcie4 pcie2 x1 (option1): pcie0 pcie2 x1 (option2): pcie2 usb3 port 0: pcie0 usb3 port 1 (option 1): pcie1 usb3 port 1 (option 2): sata0 sata: sata0 Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 6月, 2015 1 次提交
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由 Masahiro Yamada 提交于
Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NLee Jones <lee@kernel.org> Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: NRay Jui <rjui@broadcom.com> Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com> Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: NWei Chen <Wei.Chen@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 01 6月, 2015 2 次提交
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由 Jon Hunter 提交于
Commit e5b3b2d9 ("pinctrl: allows not to define the get_group_pins operation") allows pin controllers not to register the get_group_pins() function. However, a side-effect of not registering this function is that pins are not allocated and potentially multiple devices could attempt to configure the same pins [1]. Although this problem exists in the pinctrl core, because only a few devices are impacted by this, fix this for tegra-xusb by adding the get_group_pins() function. Please note that in addition to adding the get_group_pins() functions the pins/lanes for the tegra-xusb also need to be registered when calling pinctrl_register(). This also allows the current pinmux state to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad controller. [1] http://www.spinics.net/lists/linux-gpio/msg05810.htmlSigned-off-by: NJon Hunter <jonathanh@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jon Hunter 提交于
The structure tegra_xusb_padctl_group is defined but never used and so remove this. Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 11月, 2014 1 次提交
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由 Heikki Krogerus 提交于
The users of the old method are now converted to the new one. Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com> [ kishon@ti.com : made phy-berlin-usb.c and phy-miphy28lp.c to use the updated devm_phy_create API.] Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
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- 28 10月, 2014 1 次提交
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由 Thierry Reding 提交于
The pinctrl config helpers make a separate copy of the configuration, so callers must make sure to free any dynamically allocated memory that was used to store it. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 04 9月, 2014 1 次提交
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由 Linus Walleij 提交于
commit 2243a87d "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: NFan Wu <fwu@marvell.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 17 8月, 2014 2 次提交
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由 Dan Carpenter 提交于
There is a cut and paste bug so we test the wrong variable. "err" is never less than zero at this point. Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dan Carpenter 提交于
This shoudld be ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()". Fixes: dc0a3938 ('pinctrl: Add NVIDIA Tegra XUSB pad controller support') Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 7月, 2014 1 次提交
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由 Thierry Reding 提交于
The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads that lanes can be assigned to in order to support a variety of interface options: USB 2.0, USB 3.0, PCIe and SATA. In addition to the pin controller used to assign lanes to pads two PHYs are exposed to allow the bricks for PCIe and SATA to be powered up and down by PCIe and SATA drivers. Tested-by: NMikko Perttunen <mperttunen@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NThierry Reding <treding@nvidia.com>
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