Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
大约 1 年 前同步成功

通知 158
Star 36
Fork 7
cloud-kernel
cloud-kernel

体验新版 GitCode，发现更多精彩内容 >>

切换分支/标签
  1. 28 2月, 2012 1 次提交
  3. 25 2月, 2012 18 次提交
  5. 24 2月, 2012 21 次提交
    • B
      PCI: collapse pcibios_resource_to_bus · fb127cb9
      由 Bjorn Helgaas 提交于 
      Everybody uses the generic pcibios_resource_to_bus() supplied by the core
now, so remove the ARCH_HAS_GENERIC_PCI_OFFSETS used during conversion.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      fb127cb9
    • B
      xtensa/PCI: get rid of device resource fixups · 4ba2aef3
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: Chris Zankel <chris@zankel.net>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      4ba2aef3
    • B
      sparc/PCI: get rid of device resource fixups · ac1edcc5
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

N.B. Leon apparently never uses initial BAR values, so it didn't matter
that we never fixed up the I/O resources from bus address to CPU addresses.

Other sparc uses pci_of_scan_bus(), which sets device resources directly
to CPU addresses, not bus addresses, so it didn't need pcibios_fixup_bus()
either.  But by telling the core about the offsets, we can nuke
pcibios_resource_to_bus().

CC: "David S. Miller" <davem@davemloft.net>
CC: sparclinux@vger.kernel.org
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      ac1edcc5
    • B
      sh/PCI: get rid of device resource fixups · 7fa6a50e
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      7fa6a50e
    • B
      powerpc/PCI: get rid of device resource fixups · 6c5705fe
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      6c5705fe
    • B
      parisc/PCI: get rid of device resource fixups · 39c2462e
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: linux-parisc@vger.kernel.org
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      39c2462e
    • B
      mn10300/PCI: get rid of device resource fixups · 4b84b6e9
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: David Howells <dhowells@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      4b84b6e9
    • B
      mips/PCI: get rid of device resource fixups · 96a6b9ad
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses
on PCI because the GT-64111 doesn't do any address translation, so we have
this:

  CPU I/O port addresses		[io 0x0000-0xffffff]
  PCI bus I/O port addresses	[io 0x10000000-0x10ffffff]

Legacy-mode IDE controllers start out with the legacy bus addresses, e.g.,
0x1f0, assigned by pci_setup_device().  These are outside the range of
addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources()
converted them to CPU addresses anyway by adding io_offset.  Therefore, we
had to pre-adjust them in cobalt_legacy_ide_fixup().

With io_offset = 0xf0000000, we had this:

  res->start = 0x1f0	initialized in pci_setup_device()
  res->start = 0x100001f0	-= io_offset in cobalt_legacy_ide_fixup()
  res->start = 0x1f0	+= io_offset in pcibios_fixup_device_resources()

The difference after this patch is that the generic pci_bus_to_resource()
only adds the offset if the bus address is inside a host bridge window.
Since 0x1f0 is not a valid bus address and is not inside any windows, it is
unaffected, so we now have this:

  region->start = 0x1f0	initialized in pci_setup_device()
  res->start = 0x1f0	no offset by pci_bus_to_resource()

That means we can remove both pcibios_fixup_device_resources() and
cobalt_legacy_ide_fixup().

I would *rather* set the host bridge offset to zero (which corresponds
to what the GT-64111 actually does), and have both CPU and PCI addresses
of [io 0x10000000-0x10ffffff].  However, that would require changes to
generic code that assumes legacy I/O addresses, such as pic1_io_resource
([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup.

Of course, none of this changes the fact that references to I/O port
0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus.
Fortunately the VT82C586 IDE controller only decodes the low 24 address
bits, so it does work.

CC: Ralf Baechle <ralf@linux-mips.org>
CC: Yoichi Yuasa <yuasa@linux-mips.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      96a6b9ad
    • B
      microblaze/PCI: get rid of device resource fixups · aa23bdc0
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: Michal Simek <monstr@monstr.eu>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      aa23bdc0
    • B
      ia64/PCI: get rid of device resource fixups · 10d1cd2b
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: Tony Luck <tony.luck@intel.com>
CC: Jack Steiner <steiner@sgi.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      10d1cd2b
    • B
      ia64/PCI: SN: convert to pci_scan_root_bus() for correct root bus resources · f920b55d
      由 Bjorn Helgaas 提交于 
      Convert from pci_scan_bus() to pci_scan_root_bus().  Supply the root
bus resources from bussoft.  When we move the resource adjustment from
pcibios_fixup_resources() to the PCI core, it will be important to have
the root bus resources correct from the beginning.

CC: Tony Luck <tony.luck@intel.com>
CC: Jack Steiner <steiner@sgi.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      f920b55d
    • B
      arm/PCI: get rid of device resource fixups · 9f786d03
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      9f786d03
    • B
      alpha/PCI: get rid of device resource fixups · c04d9e35
      由 Bjorn Helgaas 提交于 
      Tell the PCI core about host bridge address translation so it can take
care of bus-to-resource conversion for us.

CC: linux-alpha@vger.kernel.org
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      c04d9e35
    • B
      PCI: add generic pcibios_resource_to_bus() · 36a66cd6
      由 Bjorn Helgaas 提交于 
      This replaces the generic versions of pcibios_resource_to_bus() and
pcibios_bus_to_resource() in asm-generic/pci.h with versions that use
pci_resource_to_bus() and pci_bus_to_resource().

The replacements are equivalent except that they can apply host
bridge window offsets when the arch has supplied them by using
pci_add_resource_offset().

Each arch can convert to using pci_add_resource_offset() individually by
removing its device resource fixups from pcibios_fixup_bus() and supplying
ARCH_HAS_GENERIC_PCI_OFFSETS.  ARCH_HAS_GENERIC_PCI_OFFSETS can be removed
after all have converted.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      36a66cd6
    • B
      PCI: convert bus addresses to resource when reading BARs · 5bfa14ed
      由 Bjorn Helgaas 提交于 
      Some PCI host bridges translate CPU addresses to PCI bus addresses.
Previously, we initialized pci_dev resources with PCI bus addresses,
then converted them to CPU addresses later in arch-specific code
(pcibios_fixup_resources()), which leaves a window of time where the
pci_dev resources are incorrect.

This patch adds support in the core for this address translation.
When the arch creates the root bus, it can supply the host bridge
address translation information, and the core can use it to set the
pci_dev resources correctly from the beginning.

This gives us a way to fix the problem that quirks that run between device
discovery and pcibios_fixup_resources() fail because they use pci_dev
resources that haven't been converted.  The reference below is to one
such problem that affected ARM and ia64.

Note that this patch has no effect until an arch starts using
pci_add_resource_offset() with a non-zero offset: before that, all
all host bridge windows have a zero offset and pci_bus_to_resource()
copies the pci_bus_region directly to the struct resource.

Reference: https://lkml.org/lkml/2009/10/12/405Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      5bfa14ed
    • B
      PCI: add struct pci_host_bridge_window with CPU/bus address offset · 0efd5aab
      由 Bjorn Helgaas 提交于 
      Some PCI host bridges apply an address offset, so bus addresses on PCI are
different from CPU addresses.  This patch adds a way for architectures to
tell the PCI core about this offset.  For example:

    LIST_HEAD(resources);
    pci_add_resource_offset(&resources, host->io_space, host->io_offset);
    pci_add_resource_offset(&resources, host->mem_space, host->mem_offset);
    pci_scan_root_bus(parent, bus, ops, sysdata, &resources);
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      0efd5aab
    • B
      PCI: add struct pci_host_bridge and a list of all bridges found · 5a21d70d
      由 Bjorn Helgaas 提交于 
      This adds a list of all PCI host bridges we find and a way to look up
the host bridge from a pci_dev.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      5a21d70d
    • B
      PCI: don't publish new root bus until it's fully initialized · a5390aa6
      由 Bjorn Helgaas 提交于 
      When pci_create_root_bus() adds the new struct pci_bus to the global
pci_root_buses list, the bus becomes visible to other parts of the
kernel, so it should be fully initialized.

This patch delays adding the bus to the pci_root_buses list until after
all the struct pci_bus initialization is finished.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      a5390aa6
    • B
      PCI: make pci_flags non-weak · 844393f4
      由 Bjorn Helgaas 提交于 
      No architecture defines its own pci_flags, so the core symbol does not
need to be weak.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      844393f4
    • B
      unicore32/PCI: use pci_flags PCI_PROBE_ONLY instead of arm-specific flag · b9c40b07
      由 Bjorn Helgaas 提交于 
      CC: Guan Xuetao <gxt@mprc.pku.edu.cn>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      b9c40b07
    • B
      powerpc/PCI: replace pci_probe_only with pci_flags · 673c9756
      由 Bjorn Helgaas 提交于 
      We already use pci_flags, so this just sets pci_flags directly and removes
the intermediate step of figuring out pci_probe_only, then using it to set
pci_flags.

The PCI core provides a pci_flags definition (currently __weak), so drop
the powerpc definitions in favor of that.

CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: linuxppc-dev@lists.ozlabs.org
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      673c9756