Document RZ/G2M (R8A774A1) SoC bindings.
Reviewed-by: NBiju Das <biju.das@bp.renesas.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

'interrupt-parent' is often documented as part of define bindings, but
it is really outside the scope of a device binding. It's never required
in a given node as it is often inherited from a parent node. Or it can
be implicit if a parent node is an 'interrupt-controller' node. So
remove it from all the binding files.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NRob Herring <robh@kernel.org>

Document R-Car V3H (AKA R8A77980) SoC bindings.
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Renesas RZ/G SoC have the R-Car gen2 compatible IRQC interrupt
controllers. Document RZ/G1C (also known as R8A77470) SoC bindings.
Reviewed-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The interrupt controller of the JZ4725B works the same way as the other
JZ SoCs from Ingenic; so we just add a new compatible string.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Multiple binding documents have various forms of unbalanced quotation
marks. Fix them.
Signed-off-by: NJonathan Neuschäfer <j.neuschaefer@gmx.net>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Exti controller has been differently integrated on stm32mp1 SoC.
A parent irq has only one external interrupt. A hierachy domain could
be used. Handlers are call by parent, each parent interrupt could be
masked and unmasked according to the needs.
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Update the dt-binding documentation to support new compatible string
for the GPIO interrupt controller which found in Amlogic's Meson-AXG SoC.
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The double quotes seems not ASCII type, fix it here.
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Add the required properties to support the MBI feature on GICv3.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-10-marc.zyngier@arm.com

Add the Device Tree binding documentation for the Microsemi Ocelot
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)

The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.

Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.

So long and thanks for all the fish!
Signed-off-by: NJesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add device binding documentation for the PDC Interrupt controller on
QCOM SoC's like the SDM845. The interrupt-controller can be used to
sense edge low interrupts and wakeup interrupts when the GIC is
non-operational.

Cc: devicetree@vger.kernel.org
Signed-off-by: NArchana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: NLina Iyer <ilina@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Document support for the Interrupt Controller for Externel Devices
(INTC-EX) in the Renesas M3-N (r8a77965) SoC.

No driver update is needed.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Link: https://lkml.kernel.org/r/1519658712-22910-1-git-send-email-geert%2Brenesas@glider.be

This patch adds an irqchip driver document for the Andestech Internal Vector
Interrupt Controller.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NGreentime Hu <greentime@andestech.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add documentation for DT binding of Goldfish PIC driver. The compatible
string used by OS for binding the driver is "google,goldfish-pic".
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMiodrag Dinic <miodrag.dinic@mips.com>
Signed-off-by: NGoran Ferenc <goran.ferenc@mips.com>
Signed-off-by: NAleksandar Markovic <aleksandar.markovic@mips.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This increases the interrupt cells for the 1st level interrupt controller
binding in order to describe the polarity like on the other ARM platforms.
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Improve the binding example by removing all the leading 0x to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading "0x"

Converted using the following command:

find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ ])\@0x([0-9a-f])/$1\@$2/g' {} +

This is a follow up to commit 48c926cdSigned-off-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Improve the binding example by removing all the leading zeros to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading 0s

Converted using the following command:

perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"`

Some unnecessary changes were manually fixed.
Signed-off-by: NMarco Franchi <marco.franchi@nxp.com>
Signed-off-by: NRob Herring <robh@kernel.org>

This patch updates stm32-exti documentation with stm32h7-exti
compatible string.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Add a description of the External Interrupt Unit (EXIU) interrupt
controller as found on the Socionext SynQuacer SoC.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
architecture specification:

  https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf

Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing.  This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.

Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: NStafford Horne <shorne@gmail.com>

Meson8 uses the same GPIO interrupt controller IP block as the other
Meson SoCs. A total of 134 pins can be spied on, which is the sum of:
- 22 pins on bank GPIOX
- 17 pins on bank GPIOY
- 30 pins on bank GPIODV
- 10 pins on bank GPIOH
- 15 pins on bank GPIOZ
- 7 pins on bank CARD
- 19 pins on bank BOOT
- 14 pins in the AO domain
Acked-by: NKevin Hilman <khilman@baylibre.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This commit adds the device tree bindings description for Amlogic's GPIO
interrupt controller available on the meson8b, gxbb and gxl SoC families

Cc: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The Socionext Synquacer SoC's implementation of GICv3 has a so-called
'pre-ITS', which maps 32-bit writes targeted at a separate window of
size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device
ID taken from bits [device_id_bits + 1:2] of the window offset.
Writes that target GITS_TRANSLATER directly are reported as originating
from device ID #0.

So add a workaround for this. Given that this breaks isolation, clear
the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Add the initialization of the generic irq chip for the BCM7271 L2
interrupt controller.  This controller only supports level
interrupts and uses the "brcm,bcm7271-l2-intc" compatibility
string.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDoug Berger <opendmb@gmail.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Document support for the Interrupt Controller for Externel Devices
(INTC-EX) in the Renesas M3-W (r8a7796), V3M (r8a77970), and D3
(r8a77995) SoCs.

No driver update is needed.
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Currently, the examples are using 2MB for the ITS size. Per the
specification (section 8.18 in ARM IHI 0069D), the ITS address map is
128KB.

Update the examples to match the specification.
Signed-off-by: NJulien Grall <julien.grall@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The ls1012a implements only 1 MSI controller, and it is the same as
ls1043a.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NMinghuan Lian <minghuan.Lian@nxp.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>

A MSI controller of LS1043a v1.0 only includes one MSIR and
is assigned one GIC interrupt. In order to support affinity,
LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts.
But the MSIR has the different offset and only supports 8 MSIs.
The bits between variable bit_start and bit_end in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

UniPhier SoCs contain AIDET (ARM Interrupt Detector).  This is intended
to provide additional features that are not covered by GIC.  The main
purpose is to provide logic inverter to support low level and falling
edge trigger types for interrupt lines from on-board devices.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.
Signed-off-by: NYT Shen <yt.shen@mediatek.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

This commit adds the Device Tree binding documentation for the Marvell
ICU interrupt controller, which collects wired interrupts from the
devices located into the CP110 hardware block of Marvell Armada 7K/8K,
and converts them into SPI interrupts in the GIC located in the AP
hardware block, using the GICP extension.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The Devicetree Specification has superseded the ePAPR as the
base specification for bindings.  Update files in Documentation
to reference the new document.

First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.

Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
   Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
   Documenation/virtual/kvm/api.txt
   Documenation/virtual/kvm/ppc-pv.txt
Signed-off-by: NFrank Rowand <frank.rowand@sony.com>
Signed-off-by: NRob Herring <robh@kernel.org>

This commit adds the Device Tree binding documentation for the Marvell
GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
using memory transactions. It is used by the ICU unit in the Marvell
CP110 block to turn wired interrupts inside the CP into SPI interrupts
at the GIC level in the AP.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Added device tree binding documentation for Aspeed I2C Interrupt
Controller.
Signed-off-by: NBrendan Higgins <brendanhiggins@google.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

In addition to introducing the new compatible string the bindings
description is reworked to be more generic.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The A31 and later have an R_INTC block which handles the NMI interrupt
pin on the SoC. This interrupt pin is used by the external PMIC to
signal interrupts to the SoC.

While this hardware block is undocumented, the interrupt offsets
combined with the register regions for the existing "sun6i-a31-sc-nmi"
compatible line up with the old interrupt controller found on the A10.
Experiments show that only the first 32 interrupt lines can be enabled,
and only the first (NMI) interrupt is actually connected.

This patch adds a new, properly named compatible for the A31 R_INTC
block, which requires the register region to be properly aligned to
the block boundary. For comparison, the old "sun6i-a31-sc-nmi"
compatible had its register region aligned with the first used
register. This didn't match up with the memory map in the SoC's
datasheet/user manual.

Since the new compatible supercedes the old one, deprecate the old one.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>