1. 19 4月, 2016 1 次提交
  2. 12 2月, 2016 6 次提交
  3. 31 10月, 2015 1 次提交
  4. 12 8月, 2015 2 次提交
  5. 11 8月, 2015 2 次提交
  6. 13 5月, 2015 2 次提交
    • C
      mfd: axp20x: Enable AXP22X regulators · 6d4fa89d
      Chen-Yu Tsai 提交于
      Now that the axp20x-regulators driver supports different variants of the
      AXP family, we can enable regulator support for AXP22X without the risk
      of incorrectly configuring regulators.
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      6d4fa89d
    • B
      mfd: axp20x: Add AXP22x PMIC support · f05be589
      Boris BREZILLON 提交于
      Add support for the AXP22x PMIC devices to the existing AXP20x driver.
      This includes the AXP221 and AXP223, which are identical except for
      the external data bus. Only AXP221 is added for now. AXP223 will be
      added after it's Reduced Serial Bus (RSB) interface is supported.
      
      AXP22x defines a new set of registers, power supplies and regulators,
      but most of the API is similar to the AXP20x ones.
      
      A new irq chip definition is used, even though the available interrupts
      on AXP22x is a subset of those on AXP20x. This is done so the interrupt
      numbers match those on the datasheet.
      
      This patch only enables the interrupts, system power-off function, and PEK
      sub-device. The regulator driver must first support different variants
      before we enable it from the mfd driver.
      Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
      [wens@csie.org: fix interrupts and move regulators to separate patch]
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      f05be589
  7. 09 4月, 2015 1 次提交
  8. 30 3月, 2015 1 次提交
  9. 08 3月, 2015 1 次提交
  10. 04 3月, 2015 1 次提交
  11. 27 11月, 2014 1 次提交
  12. 26 11月, 2014 1 次提交
  13. 18 11月, 2014 1 次提交
    • J
      mfd/axp20x: avoid irq numbering collision · ff3bbc5c
      Jacob Pan 提交于
      IRQ numbers in axp20x devices are defined with high-order bit first
      in each IRQ enable/status registers. On Intel platforms it is more
      common to number IRQs with least significant bit first. Therefore,
      sharing IRQ# between the two is very difficult. Since AXP288 is a
      customized PMIC for Intel platform and the amount of shared IRQs are
      very small, we use separate IRQ numbering. This also fixes collision
      and a duplicate in WBTO interrupt.
      
      e.g. For the 16 interrupts controlled in IRQ enabled registers 1 & 2,
      on axp20x for ARM, the PMIC local IRQ numbers and register bits are
      mapped as:
      IRQ#:  0  1  2  3  4  5  6  7      8  9 10 11 12 13 14 15
      ---------------------------------------------------------
      ARM:   7  6  5  4  3  2  1  0      7  6  5  4  3  2  1  0
      Intel: 0  1  2  3  4  5  6  7      0  1  2  3  4  5  6  7
      Signed-off-by: NTodd Brandt <todd.e.brandt@linux.intel.com>
      Signed-off-by: NJacob Pan <jacob.jun.pan@linux.intel.com>
      Acked-by: NJonathan Cameron <jic23@kernel.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      ff3bbc5c
  14. 07 10月, 2014 1 次提交
  15. 26 9月, 2014 1 次提交
  16. 03 6月, 2014 1 次提交