1. 07 11月, 2017 1 次提交
  2. 02 11月, 2017 16 次提交
  3. 01 11月, 2017 1 次提交
    • D
      mmc: dw_mmc: Fix the DTO timeout calculation · 9d9491a7
      Douglas Anderson 提交于
      Just like the CTO timeout calculation introduced recently, the DTO
      timeout calculation was incorrect.  It used "bus_hz" but, as far as I
      can tell, it's supposed to use the card clock.  Let's account for the
      div value, which is documented as 2x the value stored in the register,
      or 1 if the register is 0.
      
      NOTE: This was likely not terribly important until commit 16a34574
      ("mmc: dw_mmc: remove the quirks flags") landed because "DIV" is
      documented on Rockchip SoCs (the ones that used to define the quirk)
      to always be 0 or 1.  ...and, in fact, it's documented to only be 1
      with EMMC in 8-bit DDR52 mode.  Thus before the quirk was applied to
      everyone it was mostly OK to ignore the DIV value.
      
      I haven't personally observed any problems that are fixed by this
      patch but I also haven't tested this anywhere with a DIV other an 0.
      AKA: this problem was found simply by code inspection and I have no
      failing test cases that are fixed by it.  Presumably this could fix
      real bugs for someone out there, though.
      
      Fixes: 16a34574 ("mmc: dw_mmc: remove the quirks flags")
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      9d9491a7
  4. 30 10月, 2017 22 次提交