1. 03 7月, 2012 1 次提交
  2. 29 6月, 2012 1 次提交
    • A
      drm/radeon: fix VM page table setup on SI · c21b328e
      Alex Deucher 提交于
      Cayman and trinity allow for variable sized VM page
      tables, but SI requires that all page tables be the
      same size.  The current code assumes variablely sized
      VM page tables so SI may end up with part of each page
      table overlapping with other memory which could end
      up being interpreted by the VM hw as garbage.
      
      Change the code to better accomodate SI.  Allocate enough
      space for at least 2 full page tables and always set
      last_pfn to max_pfn on SI so each VM is backed by a full
      page table.  This limits us to only 2 VMs active at any
      given time on SI.  This will be rectified and the code can
      be reunified once we move to two level page tables.
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Reviewed-by: NJerome Glisse <jglisse@redhat.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      c21b328e
  3. 28 6月, 2012 1 次提交
  4. 27 6月, 2012 1 次提交
  5. 26 6月, 2012 1 次提交
    • B
      drm/nouveau/fbcon: using nv_two_heads is not a good idea · 9bd0c15f
      Ben Skeggs 提交于
      nv_two_heads() was never meant to be used outside of pre-nv50 code.  The
      code checks for >= NV_10 for 2 CRTCs, then downgrades a few specific
      chipsets to 1 CRTC based on (pci_device & 0x0ff0).
      
      The breakage example seen is on GTX 560Ti, with a pciid of 0x1200, which
      gets detected as an NV20 (0x020x) with 1 CRTC by nv_two_heads(), causing
      memory corruption because there's actually 2 CRTCs..
      
      This switches fbcon to use the CRTC count directly from the mode_config
      structure, which will also fix the same issue on Kepler boards which have
      4 CRTCs.
      Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      9bd0c15f
  6. 25 6月, 2012 1 次提交
    • D
      drm/udl: Make sure to get correct endian keys from vendor descriptor · d42f0349
      Dave Airlie 提交于
      This is a port of
      commit b49f184b
      Author: Ben Collins <bcollins@ubuntu.com>
      from udlfb to udl kms driver.
      
      The driver was not using le16_to_cpu when reading keys from the vendor
      descriptor, causing incorrect parsing. Mainly, sku_pixel_limit was not
      being parsed on big-endian systems. This would result in a blank screen
      on big-endian CPUs where the DL chips's max mode was smaller than the
      monitor's native mode.
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      d42f0349
  7. 23 6月, 2012 2 次提交
    • T
      drm/i915: Fix eDP blank screen after S3 resume on HP desktops · 6db65cbb
      Takashi Iwai 提交于
      This patch fixes the problem on some HP desktop machines with eDP
      which give blank screens after S3 resume.
      
      It turned out that BLC_PWM_CPU_CTL must be written after
      BLC_PWM_CPU_CTL2.  Otherwise it doesn't take effect on these
      SNB machines.
      
      Tested with 3.5-rc3 kernel.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49233
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      6db65cbb
    • D
      drm/i915: rip out the PM_IIR WARN · 58bf8062
      Daniel Vetter 提交于
      After banging my head against this for the past few months, I still
      don't see how this could possible race under the premise that once an
      irq bit is masked in PM_IMR and reset in PM_IIR it won't show up again
      until we unmask it in PM_IMR.
      
      Still, we have reports of this being seen in the wild. Now Bspec has
      this little bit of lovely language in the PMIIR register:
      
      Public SNB Docs, Vol3Part2, 2.5.14 "PMIIR":
      
      "For each bit, the IIR can store a second pending interrupt if two or
      more of the same interrupt conditions occur before the first condition
      is cleared. Upon clearing the interrupt, the IIR bit will momentarily
      go low, then return high to indicate there is another interrupt
      pending."
      
      Now if we presume that PMIMR only prevent new interrupts from being
      queued, we could easily end up masking an interrupt and clearing it,
      but the 2nd pending interrupt setting the bit in PMIIR right away
      again. Which leads, the next time the irq handler runs, to hitting the
      WARN.
      
      Also, no bad side effects of this have ever been reported. And we've
      tracked down our issues with the gpu turbo getting stuck to bogus
      interrupt generation limits in th RPLIMIT register.
      
      So let's just rip out this WARN as bogus and call it a day. The only
      shallow thing here is that this 2-deep irq queue in the hw makes you
      wonder how racy the windows irq handler is ...
      
      Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42907
      Cc: stable@vger.kernel.org
      Acked-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      58bf8062
  8. 21 6月, 2012 2 次提交
  9. 16 6月, 2012 12 次提交
  10. 12 6月, 2012 1 次提交
    • T
      drm/ttm: Fix buffer object metadata accounting regression v2 · a393c730
      Thomas Hellstrom 提交于
      A regression was introduced in the 3.3 rc series, commit
      "drm/ttm: simplify memory accounting for ttm user v2",
      causing the metadata of buffer objects created using the ttm_bo_create()
      function to be accounted twice.
      That causes massive leaks with the vmwgfx driver running for example
      SpecViewperf Catia-03 test 2, eventually killing the app.
      
      Furthermore, the same commit introduces a regression where
      metadata accounting is leaked if a buffer object is
      initialized with an illegal size. This is also fixed with this commit.
      
      v2: Fixed an error path and removed an unused variable.
      Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
      Reviewed-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: Jerome Glisse <jglisse@redhat.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      a393c730
  11. 11 6月, 2012 1 次提交
    • J
      drm/radeon: fix tiling and command stream checking on evergreen v3 · d2609875
      Jerome Glisse 提交于
      Fix regresson since the introduction of command stream checking on
      evergreen (thread referenced below). Issue is cause by ddx allocating
      bo with formula width*height*bpp while programming the GPU command
      stream with ALIGN(height, 8). In some case (where page alignment does
      not hide the extra size bo should be according to height alignment)
      the kernel will reject the command stream.
      
      This patch reprogram the command stream to slice - 1 (slice is
      a derivative value from height) which avoid rejecting the command
      stream while keeping the value of command stream checking from a
      security point of view.
      
      This patch also fix wrong computation of layer size for 2D tiled
      surface. Which should fix issue when 2D color tiling is enabled.
      This dump the radeon KMS_DRIVER_MINOR so userspace can know if
      they are on a fixed kernel or not.
      
      https://lkml.org/lkml/2012/6/3/80
      https://bugs.freedesktop.org/show_bug.cgi?id=50892
      https://bugs.freedesktop.org/show_bug.cgi?id=50857
      
      !!! STABLE need a custom version of this patch for 3.4 !!!
      
      v2: actually bump the minor version and add comment about stable
      v3: do compute the height the ddx was trying to use
      
      [airlied: drop left over debug]
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      d2609875
  12. 09 6月, 2012 1 次提交
    • L
      Revert "drm/i915/crt: Do not rely upon the HPD presence pin" · 8f53369b
      Linus Torvalds 提交于
      This reverts commit 9e612a00.
      
      It incorrectly finds VGA connectors where none are attached, apparently
      not noticing that nothing replied to the EDID queries, and happily using
      the default EDID modes that have nothing to do with actual hardware.
      
      That in turn then causes X to fall down to the lowest common
      denominator, which is usually the default 1024x768 mode that is in the
      default EDID and pretty much anything supports).
      
      I'd suggest that if not relying on the HDP pin, the code should at least
      check whether it gets valid EDID data back, rather than just assume
      there's something on the VGA connector.
      
      Cc: Dave Airlie <airlied@linux.ie>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      8f53369b
  13. 07 6月, 2012 1 次提交
  14. 06 6月, 2012 1 次提交
  15. 05 6月, 2012 13 次提交