1. 21 8月, 2012 1 次提交
    • D
      drm/i915: use hsw rps tuning values everywhere on gen6+ · 1ee9ae32
      Daniel Vetter 提交于
      James Bottomley reported [1] a massive power regression, due to the
      enabling of semaphores by default in 3.5. A workaround for him is to
      again disable semaphores. And indeed, his system has a very hard time
      to enter rc6 with semaphores enabled.
      
      Ben Widawsky run around with a kill-a-watt a lot and noticed:
      - There are indeed a few rare systems that seem to have a hard time
        entering rc6 when desktop-idle.
      - One machine, The Indestructible Toshiba regressed in this behaviour
        between 3.5 and 3.6 in a merge commit! So rc6 behaviour with the
        current setting seems to be highly timing dependent and not robust
        at all.
      - The behaviour James reported wrt semaphores seems to be a freak
        timing thing that only happens on his specific machine, confirming
        that enabling semaphores shouldn't reduce rc6 residency.
      
      Now furthermore the Google ChromeOS guys reported [2] a while ago that
      at least on some machines a simply a blinking cursor can keep the gpu
      turbo at the highest frequency. This is because the current rps limits
      used on snb/ivb are highly asymmetric.
      
      On the theory that gpu turbo and rc6 tuning values are related, we've
      tried whether the much saner looking (since much less asymmetric) rps
      tuning values used for hsw would also help entering rc6 more robustly.
      
      And it seems to mostly work, and we don't really have the resources to
      through-roughly tune things in any better way: The values from the
      ChromeOS ppl seem to fare a bit worse for James' machine, so I guess
      we better stick with something vpg (the gpu hw/windows group)
      provided, hoping that they've done their jobs.
      
      Reference[1]: http://lists.freedesktop.org/archives/dri-devel/2012-July/025675.html
      Reference[2]: http://lists.freedesktop.org/archives/intel-gfx/2012-July/018692.html
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53393Tested-by: NBen Widawsky <ben@bwidawsk.net>
      Cc: stable@vger.kernel.org
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      1ee9ae32
  2. 17 8月, 2012 5 次提交
  3. 14 8月, 2012 9 次提交
  4. 13 8月, 2012 20 次提交
  5. 12 8月, 2012 2 次提交
    • D
      drm/i915: ignore eDP bpc settings from vbt · 4344b813
      Daniel Vetter 提交于
      This has originally been introduced to not oversubscribe the dp links
      in
      
      commit 885a5fb5
      Author: Zhenyu Wang <zhenyuw@linux.intel.com>
      Date:   Tue Jan 12 05:38:31 2010 +0800
      
          drm/i915: fix pixel color depth setting on eDP
      
      Since then we've fixed up the dp link bandwidth calculation code and
      should now automatically fall back to 6bpc dithering. So this is
      unnecessary.
      
      Furthermore it seems to break the new MacbookPro with retina display,
      hence let's just rip this out.
      Reported-by: NBenoit Gschwind <gschwind@gnu-log.net>
      Cc: Benoit Gschwind <gschwind@gnu-log.net>
      Cc: Francois Rigaut <frigaut@gmail.com>
      Cc: Greg KH <gregkh@linuxfoundation.org>
      Cc: stable@vger.kernel.org
      Tested-by: NBenoit Gschwind <gschwind@gnu-log.net>
      Tested-by: Bernhard Froemel <froemel at vmars tuwien.ac.at>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      
      --
      
      Testing feedback highgly welcome, and thanks for Benoit for finding
      out that the bpc computations are busted.
      -Daniel
      4344b813
    • T
      drm/i915: Fix blank panel at reopening lid · 770c1231
      Takashi Iwai 提交于
      When you reopen the lid on a laptop with PCH, the panel suddenly goes
      blank sometimes.  It seems because BLC_PWM_CPU_CTL register is cleared
      to zero when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 registers are
      enabled.
      
      This patch fixes the problem by moving the call of the function setting
      BLC_PWM_CPU_CTL after enabling other two registers.
      Reported-and-tested-by: NHugh Dickins <hughd@google.com>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      770c1231
  6. 11 8月, 2012 1 次提交
  7. 10 8月, 2012 2 次提交